公开(公告)号：US5502820A

公开(公告)日：1996-03-26

申请号：US385656

申请日：1995-02-08

申请人： Atsushi Hiraishi ,  Takashi Akioka ,  Yutaka Kobayashi ,  Yuji Yokoyama ,  Masahiro Iwamura ,  Tatsumi Yamauchi ,  Shigeru Takahashi ,  Hideaki Uchida ,  Akira Ide

发明人： Atsushi Hiraishi ,  Takashi Akioka ,  Yutaka Kobayashi ,  Yuji Yokoyama ,  Masahiro Iwamura ,  Tatsumi Yamauchi ,  Shigeru Takahashi ,  Hideaki Uchida ,  Akira Ide

IPC分类号： G11C11/417 ,  G11C11/409 ,  H03K17/16 ,  H03K17/687 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/0185 ,  H03K19/08 ,  H03K19/088 ,  H03K19/0944 ,  G06F13/00

CPC分类号： H03K19/09448 ,  H03K17/164 ,  H03K19/00361

摘要： An improved buffer circuit arrangement is provided which is particularly useful for semiconductor integrated circuit semiconductor memories and microprocessors. The buffer circuit is capable of switching large loads in various types of LSIs, and features a low noise and high speed circuit operation. This is accomplished by a parallel connection of output transistors in an output buffer circuit, and by differentiating the starting time of operation between the output transistors connected in parallel without using a delay circuit. For example, differentiating the starting times can be achieved by either providing the transistors with different characteristics from one another or the driving circuits with different characteristics from one another. Another aspect of the circuit is the provision of a two-level preset arrangement which presets the output node of the circuit to predetermined values before the input signals are applied.

摘要翻译： 提供了一种改进的缓冲电路装置，其特别适用于半导体集成电路半导体存储器和微处理器。 缓冲电路能够切换各种类型的LSI中的大负载，并且具有低噪声和高速电路操作。 这通过输出缓冲器电路中的输出晶体管的并联连接，并且通过区分并联连接的输出晶体管之间的操作的起始时间而不使用延迟电路来实现。 例如，通过提供具有彼此不同特性的晶体管或具有彼此不同特性的驱动电路，可以实现区分起始时间。 电路的另一方面是提供两级预置布置，其在施加输入信号之前将电路的输出节点预设为预定值。

公开(公告)号：US5304868A

公开(公告)日：1994-04-19

申请号：US783781

申请日：1991-10-29

申请人： Yuji Yokoyama ,  Kazuyuki Miyazawa ,  Hitoshi Miwa ,  Shoji Wada

发明人： Yuji Yokoyama ,  Kazuyuki Miyazawa ,  Hitoshi Miwa ,  Shoji Wada

IPC分类号： G11C11/409 ,  G11C7/10 ,  G11C8/06 ,  G11C11/417 ,  H03K19/013 ,  H03K19/0175 ,  H03K19/0944 ,  H03K19/02 ,  G11C8/00

CPC分类号： H03K19/0136 ,  G11C7/1051 ,  G11C8/06 ,  H03K19/09448

摘要： A non-inverting buffer circuit device suited for an input buffer circuit of a semiconductor memory is provided so that the number of logic gate stages can be reduced to realize a high speed operation. The circuit is designed in such a way that an MOS transistor at an input stage drives a bipolar transistor at an output stage to produce an output. An n-channel MOS transistor and a p-channel MOS transistor connected in parallel between the base and the collector of the bipolar transistor are on/off controlled by an inverted signal of the input digital signal and a non-inverted signal thereof, respectively. In another aspect, the input buffer circuit includes an inverted signal outputting circuit, and a non-inverted signal outputting circuit in the set mode the input signal in the non-inverted state and outputting in the reset mode the signal at the prescribed potential. The inverted signal outputting circuit includes a bipolar transistor producing an output signal at its collector potential, a first switching circuit for controlling supply of a collector current to the bipolar transistor, an n-channel MOS transistor, connected in parallel between the base and the collector of the bipolar transistor, for supplying a base current to the bipolar transistor in accordance with the input signal, and a second switching circuit for controlling supply of the base current to the bipolar transistor, wherein the first switching circuit and the second switching circuit are selectively on-off controlled.

摘要翻译： 提供了适用于半导体存储器的输入缓冲电路的非反相缓冲电路装置，可以减少逻辑门级的数量，实现高速运算。 该电路被设计成使得输入级的MOS晶体管在输出级驱动双极晶体管以产生输出。 并联连接在双极型晶体管的基极和集电极之间的n沟道MOS晶体管和p沟道MOS晶体管分别通过输入数字信号的反相信号和非反相信号进行开/关控制。 在另一方面，输入缓冲电路包括反相信号输出电路和非反相信号输出电路，在设定模式下输入处于非反相状态的输入信号，并以复位模式输出处于规定电位的信号。 反相信号输出电路包括产生其集电极电位的输出信号的双极晶体管，用于控制向双极晶体管供给集电极电流的第一开关电路，并联在基极和集电极之间的n沟道MOS晶体管 用于根据输入信号向双极晶体管提供基极电流;以及第二开关电路，用于控制对双极晶体管的基极电流的供应，其中第一开关电路和第二开关电路选择性地 开关控制。