公开(公告)号：US20110156038A1

公开(公告)日：2011-06-30

申请号：US12770737

申请日：2010-04-30

Applicant: Ching-Jung Yang ,  Ke-Chih Chang ,  Kuo-Yu Huang ,  Yu-Cheng Chen

Inventor： Ching-Jung Yang ,  Ke-Chih Chang ,  Kuo-Yu Huang ,  Yu-Cheng Chen

IPC: H01L27/12 ,  H01L29/786

CPC classification number: G02F1/136213 ,  G02F1/133371 ,  G02F1/133504 ,  G02F1/133555 ,  G02F1/136227 ,  H01L27/1255

Abstract: An active device array substrate including a substrate, scan lines, data lines, active devices, a first dielectric layer, a common line, a second dielectric layer, a patterned conductive layer, a third dielectric layer, and pixel electrodes is provided. At least a part of the active devices are electrically connected to the scan lines and the data lines. The first dielectric layer covers the scan lines, the data lines and the active devices. The common line is disposed on the first dielectric layer. The second dielectric layer covers the common line and the first dielectric layer. The patterned conductive layer is disposed on the second dielectric layer. The third dielectric layer covers the patterned conductive layer and the second dielectric layer. The pixel electrodes are disposed on the third dielectric layer and electrically connected to the patterned conductive layer and the active devices.

Abstract translation: 提供了包括衬底，扫描线，数据线，有源器件，第一介电层，公共线，第二电介质层，图案化导电层，第三电介质层和像素电极的有源器件阵列衬底。 有源器件的至少一部分电连接到扫描线和数据线。 第一介电层覆盖扫描线，数据线和有源器件。 公共线设置在第一电介质层上。 第二介电层覆盖公共线和第一介电层。 图案化导电层设置在第二介电层上。 第三电介质层覆盖图案化的导电层和第二介电层。 像素电极设置在第三电介质层上并电连接到图案化导电层和有源器件。

公开(公告)号：US07701007B2

公开(公告)日：2010-04-20

申请号：US11393742

申请日：2006-03-31

Applicant: Chi-Wen Chen ,  Ting-Chang Chang ,  Po-Tsun Liu ,  Kuo-Yu Huang ,  Jen-Chien Peng

Inventor： Chi-Wen Chen ,  Ting-Chang Chang ,  Po-Tsun Liu ,  Kuo-Yu Huang ,  Jen-Chien Peng

IPC: H01L27/12

CPC classification number: H01L29/66765 ,  H01L27/124 ,  H01L27/1248

Abstract: A Thin Film Transistor comprises a gate electrode formed on a substrate; a gate insulation layer covering the gate electrode; an amorphous silicon (a-Si) region disposed on the gate insulation layer and above the gate electrode; a doped a-Si region formed on the a-Si region; the source and drain metal regions separately formed on the doped a-Si region and above the gate electrode, and isolated from the a-Si region; a passivation layer formed on the gate insulation layer and covering the source, drain and data-line (DL) metal regions; and a conductive layer formed on the passivation layer. The passivation layer has a first, second and third vias for respectively exposing the partial surfaces of the source, drain and DL metal regions. The first, second and third vias are filled with the conductive layer, so that the DL and source metal regions are connected via the conductive layer.

Abstract translation: 薄膜晶体管包括形成在基板上的栅电极; 覆盖栅电极的栅极绝缘层; 设置在栅极绝缘层上和栅电极上方的非晶硅（a-Si）区; 形成在a-Si区上的掺杂a-Si区; 源极和漏极金属区域分别形成在掺杂的a-Si区域和栅电极上方，并与a-Si区域隔离; 形成在所述栅极绝缘层上并覆盖所述源极，漏极和数据线（DL）金属区域的钝化层; 以及形成在钝化层上的导电层。 钝化层具有用于分别暴露源极，漏极和DL金属区域的部分表面的第一，第二和第三通孔。 第一，第二和第三通孔填充有导电层，使得DL和源极金属区域经由导电层连接。

公开(公告)号：US20090180066A1

公开(公告)日：2009-07-16

申请号：US12111929

申请日：2008-04-29

Applicant: Chun-Hao Tung ,  Kuo-Yu Huang

Inventor： Chun-Hao Tung ,  Kuo-Yu Huang

IPC: G02F1/1343 ,  G02F1/1335 ,  G02F1/1333

CPC classification number: G02F1/133553 ,  G02F1/133555

Abstract: A pixel structure disposed on a substrate having a plurality of protrudent patterns is provided. An area where the protrudent patterns are disposed defines a first display area. The arrangement of the protrudent patterns forms a plurality of arc loci. The arc loci have a same arc center disposed at a corner of the first display area. The abovementioned protrudent patterns avails improvement of a displaying effect of the pixel structure.

Abstract translation: 提供了设置在具有多个凸起图案的基板上的像素结构。 突出图案的布置区域限定第一显示区域。 突出图案的布置形成多个弧形轨迹。 弧形轨迹具有设置在第一显示区域的角落处的相同弧中心。 上述突出图案可以改善像素结构的显示效果。

公开(公告)号：US07528466B2

公开(公告)日：2009-05-05

申请号：US11178436

申请日：2005-07-12

Applicant: Yu-Wei Liu ,  Wen-Ching Tsai ,  Kuo-Yu Huang ,  Hui-Fen Lin

Inventor： Yu-Wei Liu ,  Wen-Ching Tsai ,  Kuo-Yu Huang ,  Hui-Fen Lin

IPC: H01L21/20

CPC classification number: H01L29/4908

Abstract: A copper gate electrode, applied in a thin-film-transistor liquid crystal display (LCD) device, at least comprises a patterned copper layer formed on a glass substrate, and a barrier layer formed on the patterned copper layer. The barrier layer comprises at least one of nitrogen and phosphorus, or comprises an alloy formularized as M1M2R wherein M1 is cobalt (Co) or molybdenum (Mo), M2 is tungsten (W), molybdenum (Mo), rhenium (Re) or vanadium (V), and R is boron (B) or phosphorus (P).

Abstract translation: 施加在薄膜晶体管液晶显示器（LCD）装置中的铜栅电极至​​少包括形成在玻璃基板上的图案化铜层和形成在图案化铜层上的阻挡层。 阻挡层包括氮和磷中的至少一种，或包含形式为M1M2R的合金，其中M1是钴（Co）或钼（Mo），M2是钨（W），钼（Mo），铼（Re）或钒 （V），R为硼（B）或磷（P）。

公开(公告)号：US20070148563A1

公开(公告)日：2007-06-28

申请号：US11426388

申请日：2006-06-26

Applicant: Yen-Heng Huang ,  Yu-Wei Liu ,  Yu-Hsin Ting ,  Kuo-Yu Huang

Inventor： Yen-Heng Huang ,  Yu-Wei Liu ,  Yu-Hsin Ting ,  Kuo-Yu Huang

IPC: G02B5/20

CPC classification number: G02B5/201 ,  G02B5/223 ,  G02F1/133516

Abstract: A color filter and a method for fabricating the same. At least one conductive film is provided above a light shielding layer between R/G/B color filter units. The conductive film is electrically connected to an electrode layer, thereby reducing the resistance thereof.

Abstract translation: 滤色器及其制造方法。 在R / G / B滤色器单元之间的遮光层上方设置至少一个导电膜。 导电膜电连接到电极层，从而降低其电阻。

公开(公告)号：US20060246713A1

公开(公告)日：2006-11-02

申请号：US11206381

申请日：2005-08-18

Applicant: Tzeng-Guang Tsai ,  Kuo-Yu Huang ,  Hui-Fen Lin ,  Yu-Wei Liu

Inventor： Tzeng-Guang Tsai ,  Kuo-Yu Huang ,  Hui-Fen Lin ,  Yu-Wei Liu

IPC: H01L21/4763 ,  H01L29/94 ,  H01L29/76 ,  H01L31/00

CPC classification number: H01L21/76885 ,  G02F2001/136295 ,  H01L21/76834 ,  H05K3/0023 ,  H05K3/064 ,  H05K3/108 ,  H05K3/388 ,  H05K2201/0108 ,  H05K2203/0571 ,  H05K2203/0585 ,  H05K2203/0597

Abstract: The wiring line structure comprises a transparent substrate, a barrier layer, a metal layer, and a photosensitive protecting layer. The barrier layer and a metal layer are successively disposed on the transparent substrate. The photosensitive protecting layer is formed on the barrier layer and both sides of the metal layer. A method for fabricating the wiring line structure is also disclosed.

公开(公告)号：US20060138659A1

公开(公告)日：2006-06-29

申请号：US11178436

申请日：2005-07-12

Applicant: Yu-Wei Liu ,  Wen-Ching Tsai ,  Kuo-Yu Huang ,  Hui-Fen Lin

Inventor： Yu-Wei Liu ,  Wen-Ching Tsai ,  Kuo-Yu Huang ,  Hui-Fen Lin

IPC: H01L29/40 ,  H01L21/44

CPC classification number: H01L29/4908

Abstract: A copper gate electrode, applied in a thin-film-transistor liquid crystal display (LCD) device, at least comprises a patterned copper layer formed on a glass substrate, and a barrier layer formed on the patterned copper layer. The barrier layer comprises at least one of nitrogen and phosphorus, or comprises an alloy formularized as M1M2R wherein M1 is cobalt (Co) or molybdenum (Mo), M2 is tungsten (W), molybdenum (Mo), rhenium (Re) or vanadium (V), and R is boron (B) or phosphorus (P).

Abstract translation: 施加在薄膜晶体管液晶显示器（LCD）装置中的铜栅电极至​​少包括形成在玻璃基板上的图案化铜层和形成在图案化铜层上的阻挡层。 阻挡层包括氮和磷中的至少一种，或者包含配位为M 1 M 2 R 2的合金，其中M 1是钴（ Co）或钼（Mo），M 2是钨（W），钼（Mo），铼（Re）或钒（V），R是硼（B）或磷（P） 。

公开(公告)号：US20130168704A1

公开(公告)日：2013-07-04

申请号：US13483005

申请日：2012-05-29

Applicant: Kuo-Yu Huang ,  Te-Chun Huang

Inventor： Kuo-Yu Huang ,  Te-Chun Huang

IPC: H01L27/15 ,  H01L33/36

CPC classification number: H01L27/1248 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/1288 ,  H01L27/156

Abstract: A panel is disclosed, in which, a patterned semiconductor layer is formed on an insulation layer. The patterned semiconductor layer includes a portion corresponding to an electrode and another portion corresponding to a wiring trace. The portion corresponding to the electrode may be formed as, for example, a channel, and the other portion corresponding to the wiring trace may protect the wiring trace during fabrication process or in the structure from scratching or corrosion.

Abstract translation: 公开了一种面板，其中在绝缘层上形成图案化的半导体层。 图案化半导体层包括对应于电极的部分和对应于布线迹线的另一部分。 对应于电极的部分可以形成为例如通道，并且对应于布线迹线的另一部分可以在制造过程期间或在结构中保护布线迹线免受刮擦或腐蚀。

公开(公告)号：US08445911B2

公开(公告)日：2013-05-21

申请号：US12770737

申请日：2010-04-30

Applicant: Ching-Jung Yang ,  Ke-Chih Chang ,  Kuo-Yu Huang ,  Yu-Cheng Chen

Inventor： Ching-Jung Yang ,  Ke-Chih Chang ,  Kuo-Yu Huang ,  Yu-Cheng Chen

IPC: H01L29/04 ,  H01L29/10 ,  H01L31/00

CPC classification number: G02F1/136213 ,  G02F1/133371 ,  G02F1/133504 ,  G02F1/133555 ,  G02F1/136227 ,  H01L27/1255

Abstract: An active device array substrate including a substrate, scan lines, data lines, active devices, a first dielectric layer, a common line, a second dielectric layer, a patterned conductive layer, a third dielectric layer, and pixel electrodes is provided. At least a part of the active devices are electrically connected to the scan lines and the data lines. The first dielectric layer covers the scan lines, the data lines and the active devices. The common line is disposed on the first dielectric layer. The second dielectric layer covers the common line and the first dielectric layer. The patterned conductive layer is disposed on the second dielectric layer. The third dielectric layer covers the patterned conductive layer and the second dielectric layer. The pixel electrodes are disposed on the third dielectric layer and electrically connected to the patterned conductive layer and the active devices.

Abstract translation: 提供了包括衬底，扫描线，数据线，有源器件，第一介电层，公共线，第二电介质层，图案化导电层，第三电介质层和像素电极的有源器件阵列衬底。 有源器件的至少一部分电连接到扫描线和数据线。 第一介电层覆盖扫描线，数据线和有源器件。 公共线设置在第一电介质层上。 第二介电层覆盖公共线和第一介电层。 图案化导电层设置在第二介电层上。 第三电介质层覆盖图案化的导电层和第二介电层。 像素电极设置在第三电介质层上并电连接到图案化导电层和有源器件。

公开(公告)号：US08120742B2

公开(公告)日：2012-02-21

申请号：US12369757

申请日：2009-02-12

Applicant: Maw-Song Chen ,  Kuo-Yu Huang ,  Te-Chun Huang

Inventor： Maw-Song Chen ,  Kuo-Yu Huang ,  Te-Chun Huang

IPC: G02F1/1345 ,  G09G3/36 ,  H01L29/04

CPC classification number: G02F1/13394 ,  G02F1/13454 ,  G02F2001/133388

Abstract: A driving circuit and a common electrode are located within a sealant region of the first substrate, wherein the driving circuit includes switch devices and turn-line structures. The common electrode is located within the sealant region of the first substrate. The planar layer is located on the first substrate, wherein the thickness of the planar layer at the turn-line structure of the driving circuit is less than the thicknesses of other portions. The conductive layer is located on the planar layer. A second substrate having an electrode thereon is disposed opposite to the first substrate. A liquid crystal layer is located within the display region between the first substrate and the second substrate. A sealant is located within the sealant region between the first substrate and the second substrate, and conductive balls are distributed in the sealant.

Abstract translation: 驱动电路和公共电极位于第一基板的密封剂区域内，其中驱动电路包括开关装置和开关线结构。 公共电极位于第一基板的密封剂区域内。 平面层位于第一基板上，其中驱动电路的转线结构处的平面层的厚度小于其它部分的厚度。 导电层位于平面层上。 其上具有电极的第二基板设置成与第一基板相对。 液晶层位于第一基板和第二基板之间的显示区域内。 密封剂位于第一基板和第二基板之间的密封剂区域内，导电球分布在密封剂中。