公开(公告)号：US20070226531A1

公开(公告)日：2007-09-27

申请号：US11724319

申请日：2007-03-15

申请人： Joonbae Park ,  Kyeongho Lee

发明人： Joonbae Park ,  Kyeongho Lee

IPC分类号： G06F1/04

CPC分类号： H03L7/0812 ,  H03L7/08 ,  H03L7/22

摘要： Embodiments of a clock generator and a clock generating method can use a delay locked loop (DLL). In one embodiment, a clock generator can include a first oscillator to generate a first clock signal having a frequency corresponding to a control signal, a delay locked loop to generate a second clock signal having a frequency higher than that of the first clock signal, a frequency divider to receive the second clock signal to generate a third clock signal having a frequency lower than that of the second clock signal, a second oscillator to generate a fourth clock signal and a phase frequency detector to generate the control signal corresponding to a phase difference and/or a frequency difference between the third clock signal and the fourth clock signal.

摘要翻译： 时钟发生器和时钟产生方法的实施例可以使用延迟锁定环（DLL）。 在一个实施例中，时钟发生器可以包括第一振荡器以产生具有对应于控制信号的频率的第一时钟信号，延迟锁定环路以产生频率高于第一时钟信号的频率的第二时钟信号， 分频器，用于接收所述第二时钟信号以产生具有低于所述第二时钟信号的频率的第三时钟信号;产生第四时钟信号的第二振荡器和产生对应于相位差的控制信号的相位频率检测器 和/或第三时钟信号与第四时钟信号之间的频率差。

公开(公告)号：US20060152290A1

公开(公告)日：2006-07-13

申请号：US11227439

申请日：2005-09-16

申请人： Kyeongho Lee ,  Joonbae Park ,  Jeong-Woo Lee ,  Seung-Wook Lee

发明人： Kyeongho Lee ,  Joonbae Park ,  Jeong-Woo Lee ,  Seung-Wook Lee

IPC分类号： H03L7/00

CPC分类号： H03L7/113 ,  H03L7/099 ,  H03L7/18

摘要： An apparatus and method of oscillating a wideband frequency are disclosed. The apparatus includes: a frequency oscillating unit for oscillating a predetermined frequency; a phase-locked loop for comparing the oscillated frequency and a reference frequency by feed-backing the oscillated frequency from the frequency oscillating unit and fixing an oscillating frequency of the frequency oscillating unit; and a variable dividing unit for varying a division ratio to approach to a frequency band required by the oscillating frequency and dividing the oscillating frequency.

摘要翻译： 公开了一种振荡宽带频率的装置和方法。 该装置包括：用于振荡预定频率的频率振荡单元; 锁相环，用于通过从振荡单元馈送振荡频率并固定频率振荡单元的振荡频率来比较振荡频率和参考频率; 以及可变分割单元，用于改变分频比以接近振荡频率所需的频带并分频振荡频率。

公开(公告)号：US06993109B2

公开(公告)日：2006-01-31

申请号：US10231312

申请日：2002-08-30

申请人： Kyeongho Lee ,  Joonbae Park

发明人： Kyeongho Lee ,  Joonbae Park

IPC分类号： H03D3/24

CPC分类号： H03L7/0805 ,  G06F1/10 ,  H03L7/07 ,  H03L7/0812 ,  H03L7/0891 ,  H03L7/23 ,  H04B15/04 ,  H04B2215/064 ,  H04B2215/067

摘要： A clock recovery circuit and a method for reducing electromagnetic emission (EMI) and increasing an attainable clock frequency includes a spread spectrum clock (SSC) generator that receives an input clock signal and generates a frequency-modulated clock signal, and a zero-delay buffer circuit that receives and buffers said modulated clock frequency signed to generated an output clock signal. The frequency-modulated clock signal and the output clock signal are phase-aligned such that there is no phase difference between the output clock signal and the modulated frequency clock signal. The clock recovery circuit also includes a delay-locked loop (DLL) circuit that reduces related art jitter and skew characteristics, and a phase detector circuit that eliminates phase ambiguity problems of a related art phase detector.

公开(公告)号：US06781424B2

公开(公告)日：2004-08-24

申请号：US10253534

申请日：2002-09-25

申请人： Kyeongho Lee ,  Deog-Kyoon Jeong ,  Joonbae Park ,  Wonchan Kim

发明人： Kyeongho Lee ,  Deog-Kyoon Jeong ,  Joonbae Park ,  Wonchan Kim

IPC分类号： H04B118

CPC分类号： H04B1/403 ,  H03F2200/372 ,  H03H11/22 ,  H03H2011/0494 ,  H03K9/00 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/1974 ,  H04B1/18 ,  H04B1/28 ,  H04B1/40

摘要： A single chip RF communication system and method is provided including a transmitter and a receiver. The RF communication system in accordance with the present invention can include an antenna that receives/transmits RF signals, a PLL that generates multi-phase clock signals having a frequency different from a carrier frequency and a reference signal having the carrier frequency, a demodulation-mixer that mixes the received RF signals with the multi-phase clock signals having the frequency different from the carrier frequency to output signals having a frequency reduced relative to the carrier frequency, two stage amplification that amplifies a selected channel signal to a required dynamic level, and an A/D converting unit for converting the RF signals from the mixing unit into digital signals. The two stage amplification can provide the selected channel signal with sufficient gain, even when an adjacent channel signal is output by the demodulation mixer with greater amplitude or power.

摘要翻译： 提供了包括发射机和接收机的单芯片RF通信系统和方法。 根据本发明的RF通信系统可以包括接收/发射RF信号的天线，产生具有与载波频率不同的频率的多相时钟信号的PLL和具有载波频率的参考信号， 混频器将接收到的RF信号与具有与载波频率不同的频率的多相时钟信号混合以输出相对于载波频率降低的频率的信号;将所选频道信号放大到所需动态电平的两级放大， 以及用于将来自混合单元的RF信号转换为数字信号的A / D转换单元。 即使相邻信道信号由具有较大幅度或功率的解调混频器输出，两级放大可以提供所选择的信道信号足够的增益。

公开(公告)号：US06483355B1

公开(公告)日：2002-11-19

申请号：US09709637

申请日：2000-11-13

申请人： Kyeongho Lee ,  Deog-Kyoon Jeong ,  Joonbae Park ,  Wonchan Kim

发明人： Kyeongho Lee ,  Deog-Kyoon Jeong ,  Joonbae Park ,  Wonchan Kim

IPC分类号： H04B118

CPC分类号： H04B1/403 ,  H03F2200/372 ,  H03H11/22 ,  H03H2011/0494 ,  H03K9/00 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/1974 ,  H04B1/18 ,  H04B1/28 ,  H04B1/40

摘要： A single chip RF communication system and method is provided including a transmitter and a receiver. The RF communication system in accordance with the present invention can include an antenna that receives/transmits RF signals, a PLL that generates multi-phase clock signals having a frequency different from a carrier frequency and a reference signal having the carrier frequency, a demodulation-mixer that mixes the received RF signals with the multi-phase clock signals having the frequency different from the carrier frequency to output signals having a frequency reduced relative to the carrier frequency, two stage amplification that amplifies a selected channel signal to a required dynamic level, and an A/D converting unit for converting the RF signals from the mixing unit into digital signals. The two stage amplification can provide the selected channel signal with sufficient gain, even when an adjacent channel signal is output by the demodulation mixer with greater amplitude or power.

摘要翻译： 提供了包括发射机和接收机的单芯片RF通信系统和方法。 根据本发明的RF通信系统可以包括接收/发射RF信号的天线，产生具有与载波频率不同的频率的多相时钟信号的PLL和具有载波频率的参考信号， 混频器将接收到的RF信号与具有与载波频率不同的频率的多相时钟信号混合以输出相对于载波频率降低的频率的信号;将所选频道信号放大到所需动态电平的两级放大， 以及用于将来自混合单元的RF信号转换为数字信号的A / D转换单元。 即使相邻信道信号由具有较大幅度或功率的解调混频器输出，两级放大可以提供所选择的信道信号足够的增益。

公开(公告)号：US08229028B2

公开(公告)日：2012-07-24

申请号：US12034627

申请日：2008-02-20

申请人： Kyeongho Lee ,  Joonbae Park ,  Jeong Woo Lee ,  Seung-Wook Lee ,  Eal Wan Lee

发明人： Kyeongho Lee ,  Joonbae Park ,  Jeong Woo Lee ,  Seung-Wook Lee ,  Eal Wan Lee

IPC分类号： H04K1/02

CPC分类号： H04L27/3863 ,  H04L27/364

摘要： The present invention relates to an apparatus and a method for measuring an in phase and quadrature (IQ) imbalance. One embodiment according to the present general inventive concept can provide a method for measuring a Tx IQ imbalance generated in an IQ up-conversion mixer and an Rx IQ imbalance generated in an IQ down-conversion mixer, that includes measuring a first IQ imbalance corresponding to a first combination of the Rx IQ imbalance with the Tx IQ imbalance, measuring a second IQ imbalance corresponding to a second combination of the Rx IQ imbalance with the Tx IQ imbalance and obtaining the Tx IQ imbalance and the Rx IQ imbalance from the first IQ imbalance and the second IQ imbalance.

摘要翻译： 本发明涉及用于测量同相和正交（IQ）不平衡的装置和方法。 根据本发明总体构思的一个实施例可以提供一种用于测量在IQ上变频混频器中产生的Tx IQ不平衡和在IQ下变频混频器中产生的Rx IQ不平衡的方法，其包括测量对应于 Rx IQ不平衡与Tx IQ不平衡的第一组合，测量对应于Rx IQ不平衡与Tx IQ不平衡的第二组合的第二IQ不平衡，并且从第一IQ不平衡获得Tx IQ不平衡和Rx IQ不平衡 和第二个智商不平衡。

公开(公告)号：US08018990B2

公开(公告)日：2011-09-13

申请号：US12027742

申请日：2008-02-07

申请人： Kyeongho Lee ,  Joonbae Park ,  Jeong Woo Lee ,  Seung-Wook Lee ,  Eal Wan Lee

发明人： Kyeongho Lee ,  Joonbae Park ,  Jeong Woo Lee ,  Seung-Wook Lee ,  Eal Wan Lee

IPC分类号： H04B3/46

CPC分类号： H04L27/364 ,  H04L27/3863

摘要： The present general inventive concept relates to apparatuses and/or methods for measuring an in-phase and quadrature (IQ) imbalance. In one embodiment, a detector can measure an error caused by an IQ imbalance using a first IQ signal including a desired signal and a corresponding image signal by the IQ imbalance. The detector can include a derotator to derotate the first IQ signal by a first angular frequency to obtain a second IQ signal and derotate the first IQ signal by a second angular frequency to obtain a third IQ signal, a DC estimator to obtain a fourth IQ signal corresponding to a DC component of the second IQ signal and a fifth IQ signal corresponding to a DC component of the third IQ signal and a controller can determine a gain error or a phase error from the fourth IQ signal and the fifth IQ signal.

摘要翻译： 本总体发明构思涉及用于测量同相和正交（IQ）不平衡的装置和/或方法。 在一个实施例中，检测器可以通过IQ不平衡来使用包括期望信号和对应图像信号的第一IQ信号来测量由IQ不平衡引起的误差。 检测器可以包括解旋器，以将第一IQ信号扭转第一角度频率以获得第二IQ信号并且将第一IQ信号解旋第二角频率以获得第三IQ信号，DC估计器以获得第四IQ信号 对应于第二IQ信号的DC分量和对应于第三IQ信号的DC分量的第五IQ信号，并且控制器可以从第四IQ信号和第五IQ信号确定增益误差或相位误差。

公开(公告)号：US07949324B2

公开(公告)日：2011-05-24

申请号：US11819943

申请日：2007-06-29

申请人： Joonbae Park ,  Kyeongho Lee ,  Sang Hun Jung ,  Eal Wan Lee ,  In Ho Song

发明人： Joonbae Park ,  Kyeongho Lee ,  Sang Hun Jung ,  Eal Wan Lee ,  In Ho Song

IPC分类号： H04B1/26

CPC分类号： H04L27/0014 ,  H04L2027/0016 ,  H04L2027/0022

摘要： The application discloses embodiments of methods and/or systems for compensating a transmission carrier leakage of an up-conversion mixer, a tranceiving circuit or apparatus embodying the same. One embodiment of a method can include detecting an I channel DC offset DCI0 and a Q channel DC offset DCQ0 generated by a reception carrier leakage from an output of a down-conversion mixer, detecting an I channel DC offset DCI and a Q channel DC offset DCQ from the output of the down-conversion mixer while varying a compensation parameter being inputted to an up-conversion mixer that has its output coupled to an input of the down-conversion mixer to determine the compensation parameter that can reduce or minimize a transmission carrier leakage. A combination of a transmission baseband signal and the determined compensation parameter can be transmitted using the up-conversion mixer and an antenna to compensate for the transmission carrier leakage.

摘要翻译： 本申请公开了用于补偿上变频混频器，引入电路或体现其的转换电路或设备的传输载波泄漏的方法和/或系统的实施例。 方法的一个实施例可以包括从下变频混频器的输出检测I信道DC偏移DCI0和由接收载波泄漏产生的Q信道DC偏移DCQ0，检测I信道DC偏移DCI和Q信道DC偏移 DCQ从下转换混频器的输出，同时改变输入到上变频混频器的补偿参数，该上转换混频器的输出耦合到下转换混频器的输入，以确定可以减少或最小化传输载波的补偿参数 泄漏。 传输基带信号和所确定的补偿参数的组合可以使用上变频混频器和天线来传输，以补偿传输载波泄漏。

公开(公告)号：US20090028231A1

公开(公告)日：2009-01-29

申请号：US12034627

申请日：2008-02-20

申请人： Kyeongho Lee ,  Joonbae Park ,  Jeong-Woo Lee ,  Seung-Wook Lee ,  Eal Wan Lee

发明人： Kyeongho Lee ,  Joonbae Park ,  Jeong-Woo Lee ,  Seung-Wook Lee ,  Eal Wan Lee

IPC分类号： H04B17/00

CPC分类号： H04L27/3863 ,  H04L27/364

摘要： The present invention relates to an apparatus and a method for measuring an IQ imbalance. One embodiment according to the present general inventive concept can provide a method for measuring a Tx IQ imbalance generated in an IQ up-conversion mixer and an Rx IQ imbalance generated in an IQ down-conversion mixer, that includes measuring a first IQ imbalance corresponding to a first combination of the Rx IQ imbalance with the Tx IQ imbalance, measuring a second IQ imbalance corresponding to a second combination of the Rx IQ imbalance with the Tx IQ imbalance and obtaining the Tx IQ imbalance and the Rx IQ imbalance from the first IQ imbalance and the second IQ imbalance.

摘要翻译： 本发明涉及一种用于测量IQ不平衡的装置和方法。 根据本发明总体构思的一个实施例可以提供一种用于测量在IQ上变频混频器中产生的Tx IQ不平衡和在IQ下变频混频器中产生的Rx IQ不平衡的方法，其包括测量对应于 Rx IQ不平衡与Tx IQ不平衡的第一组合，测量对应于Rx IQ不平衡与Tx IQ不平衡的第二组合的第二IQ不平衡，并且从第一IQ不平衡获得Tx IQ不平衡和Rx IQ不平衡 和第二个智商不平衡。

公开(公告)号：US07436265B2

公开(公告)日：2008-10-14

申请号：US11724319

申请日：2007-03-15

申请人： Joonbae Park ,  Kyeongho Lee

发明人： Joonbae Park ,  Kyeongho Lee

IPC分类号： H03L7/06 ,  H03L7/16 ,  H03L7/18

CPC分类号： H03L7/0812 ,  H03L7/08 ,  H03L7/22

摘要： Embodiments of a clock generator and a clock generating method can use a delay locked loop (DLL). In one embodiment, a clock generator can include a first oscillator to generate a first clock signal having a frequency corresponding to a control signal, a delay locked loop to generate a second clock signal having a frequency higher than that of the first clock signal, a frequency divider to receive the second clock signal to generate a third clock signal having a frequency lower than that of the second clock signal, a second oscillator to generate a fourth clock signal and a phase frequency detector to generate the control signal corresponding to a phase difference and/or a frequency difference between the third clock signal and the fourth clock signal.

摘要翻译： 时钟发生器和时钟产生方法的实施例可以使用延迟锁定环（DLL）。 在一个实施例中，时钟发生器可以包括第一振荡器以产生具有对应于控制信号的频率的第一时钟信号，延迟锁定环路以产生频率高于第一时钟信号的频率的第二时钟信号， 分频器，用于接收所述第二时钟信号以产生具有低于所述第二时钟信号的频率的第三时钟信号;产生第四时钟信号的第二振荡器和产生对应于相位差的控制信号的相位频率检测器 和/或第三时钟信号与第四时钟信号之间的频率差。