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    STACKED SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME
    41.
    发明申请
    STACKED SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME 有权

    公开(公告)号：US20210384135A1

    公开(公告)日：2021-12-09

    申请号：US16987440

    申请日：2020-08-07

    Applicant: Intel Corporation

    Inventor： Chin Lee KUAN ,  Bok Eng CHEAH ,  Jackson Chung Peng KONG ,  Sameer SHEKHAR ,  Amit JAIN

    IPC: H01L23/538 ,  H01L23/00 ,  H01L21/48

    Abstract: According to various examples, a stacked semiconductor package is described. The stacked semiconductor package may include a package substrate. The stacked semiconductor package may also include a base die disposed on and electrically coupled to the package substrate. The stacked semiconductor package may further include a mold portion disposed on the package substrate at a periphery of the base die, the mold portion may include a through-mold interconnect electrically coupled to the package substrate. The stacked semiconductor package may further include a semiconductor device having a first section disposed on the base die and a second section disposed on the mold portion, wherein the second section of the semiconductor device may be electrically coupled to the package substrate through the through-mold interconnect.

    SEMICONDUCTOR PACKAGE WITH HYBRID MOLD LAYERS
    43.
    发明申请
    SEMICONDUCTOR PACKAGE WITH HYBRID MOLD LAYERS 有权

    公开(公告)号：US20210335698A1

    公开(公告)日：2021-10-28

    申请号：US17367684

    申请日：2021-07-06

    Applicant: Intel Corporation

    Inventor： Bok Eng CHEAH ,  Chia Chuan WU ,  Jackson Chung Peng KONG ,  Kooi Chi OOI

    IPC: H01L23/498 ,  H01L23/552 ,  H01L23/367 ,  H01L25/065 ,  H01L21/48

    Abstract: According to various examples, a device is described. The device may include a first package substrate. The device may also include a first mold layer with a first thickness. The device may also include a second mold layer with a second thickness proximal to the first mold layer. The second thickness may be larger than the first thickness. The first mold layer may include a plurality of first interconnects coupled to the first package substrate. The second mold layer may include a plurality of second interconnects configured to couple the first package substrate to a printed circuit board.

    OVER-MOLDED IC PACKAGES WITH EMBEDDED VOLTAGE REFERENCE PLANE & HEATER SPREADER
    44.
    发明申请
    OVER-MOLDED IC PACKAGES WITH EMBEDDED VOLTAGE REFERENCE PLANE & HEATER SPREADER 审中-公开

    公开(公告)号：US20180366407A1

    公开(公告)日：2018-12-20

    申请号：US15982912

    申请日：2018-05-17

    Applicant: Intel Corporation

    Inventor： Ping Ping OOI ,  Bok Eng CHEAH ,  Jackson Chung Peng KONG ,  Mooi Ling CHANG ,  Wen Wei LUM

    IPC: H01L23/522 ,  H01L23/528 ,  H01L23/50 ,  H01L23/367

    Abstract: Over-molded IC package assemblies including an embedded voltage reference plane and/or heat spreader. In some embodiments, an over-molded package assembly includes a IC chip or die coupled to one or more metal distribution layer or package substrate. A molding compound encapsulates at least the IC chip and one or more conductive layers are embedded within the molding compound. The conductive layers may include an interior portion located over the IC chip and a peripheral portion located over the redistribution layers or package substrate. The interior portion may comprise one or more heat conductive features, which may physically contact a surface of the IC chip. In some further embodiments, the peripheral portion comprises one or more electrically conductive features, which may physically contact a surface of the package redistribution layers or package substrate to convey a reference voltage. One or more conductive traces may connect the conductive features in the interior with conductive features in the periphery.

    MICRO THROUGH-SILICON VIA FOR TRANSISTOR DENSITY SCALING
    45.
    发明申请
    MICRO THROUGH-SILICON VIA FOR TRANSISTOR DENSITY SCALING 有权

    公开(公告)号：US20240429131A1

    公开(公告)日：2024-12-26

    申请号：US18824468

    申请日：2024-09-04

    Applicant: Intel Corporation

    Inventor： Bok Eng CHEAH ,  Choong Kooi CHEE ,  Jackson Chung Peng KONG ,  Wai Ling LEE ,  Tat Hin TAN

    IPC: H01L23/48 ,  H01L21/768 ,  H01L21/822 ,  H01L23/00 ,  H01L25/16

    Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.

    HYBRID SEMICONDUCTOR PACKAGE FOR IMPROVED POWER INTEGRITY
    49.
    发明公开
    HYBRID SEMICONDUCTOR PACKAGE FOR IMPROVED POWER INTEGRITY 审中-公开

    公开(公告)号：US20230187368A1

    公开(公告)日：2023-06-15

    申请号：US17548628

    申请日：2021-12-13

    Applicant: Intel Corporation

    Inventor： Seok Ling LIM ,  Bok Eng CHEAH ,  Jenny Shio Yin ONG ,  Jackson Chung Peng KONG ,  Kooi Chi OOI

    IPC: H01L23/538 ,  H01L23/13 ,  H01L21/48

    CPC classification number: H01L23/5386 ,  H01L23/13 ,  H01L23/5383 ,  H01L23/5385 ,  H01L21/4857

    Abstract: The present disclosure generally relates to an electronic assembly. The electronic assembly may include a first substrate including a first surface, an opposing second surface and a recess opening extending through the first surface. The electronic assembly may also include a power delivery mold frame including a first mold surface, an opposing second mold surface, a plurality of first metal planes and a plurality of second metal planes extending between the first and second mold surfaces, the power delivery mold frame arranged in the recess opening and coupled to the first substrate through the first mold surface. The electronic assembly may further include a second substrate including a subsequent first surface, an opposing subsequent second surface, the second substrate coupled to the power delivery mold frame through a plurality of first solder bumps and further coupled to the first substrate through a plurality of second solder bumps at the subsequent first surface.

    INTERCONNECTS BRIDGES FOR MULTI-CHIP PACKAGES
    50.
    发明申请
    INTERCONNECTS BRIDGES FOR MULTI-CHIP PACKAGES 有权

    公开(公告)号：US20230065380A1

    公开(公告)日：2023-03-02

    申请号：US17411062

    申请日：2021-08-25

    Applicant: Intel Corporation

    Inventor： Bok Eng CHEAH ,  Seok Ling LIM ,  Jenny Shio Yin ONG ,  Jackson Chung Peng KONG ,  Kooi Chi OOI

    IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L25/00

    Abstract: The present disclosure is directed to multichip semiconductor packages, and methods for making them, which includes a package substrate with an integrated bridge frame having a first horizontal portion positioned on a top surface of the package substrate, with first and second dies positioned overlapping the first horizontal portion of the bridge frame, and a second horizontal portion positioned on the bottom surface of the package substrate, with third and fourth dies positioned overlapping the second horizontal portion of the bridge frame. The bridge frame further includes first and second vertical portions separated by a portion of the package substrate positioned under the first horizontal portion of the bridge frame between the top surface and bottom surfaces of the package substrate, and a plurality of vertical interconnects adjacent to the first and second vertical portions of the bridge frame.

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