公开(公告)号：US20190229473A1

公开(公告)日：2019-07-25

申请号：US16370665

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Jaejin LEE ,  Jun LIAO ,  Xiang LI ,  Christopher E. COX

IPC: H01R13/6595 ,  H01R13/6581 ,  H05K9/00 ,  H01R12/72 ,  H05K1/11

Abstract: A device includes a printed circuit board (PCB) and a shield for the PCB. The shield can reduce high frequency electromagnetic frequency (EMF) noise generated by one or more components of the PCB. The PCB includes pads to interface with a corresponding connector. For example, for a dual inline memory module (DIMM) PCB, the PCB includes pads to insert into a DIMM connector. The shield includes a gap in its perimeter that aligns with clips in the corresponding connector. The gaps will correspond to similar features of the PCB that interface with the corresponding connector to allow the shield to attach to the PCB. The shield includes lock fingers to extend from a connector-facing edge of the shield to interface with the corresponding connector to align the shield with the corresponding connector.

公开(公告)号：US20240159829A1

公开(公告)日：2024-05-16

申请号：US18551879

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Min LIU ,  Jaemon FRANKO ,  Xia JIN ,  Xiang LI ,  Jiaqi LIU ,  Krishna SURYA

IPC: G01R31/3185

CPC classification number: G01R31/318591 ,  G01R31/31853 ,  G01R31/318547

Abstract: A processing device (30, 710) for reducing scan traffic is provided. The processing device (30, 710) comprises one or more interfaces (32, 718) configured to transmit information to at least one register access interface (759, 761) and processing circuitry (34) configured to control the one or more interfaces. Further, the processing circuitry (34) is configured to obtain register parameters of at least one functional unit (760, 762) of a processing unit (750) and to generate an improved bulk register comprising the register parameters of the at least one functional unit.

公开(公告)号：US20240145996A1

公开(公告)日：2024-05-02

申请号：US18395069

申请日：2023-12-22

Applicant: Intel Corporation

Inventor： Xiang LI ,  George VERGIS ,  James A. McCALL

IPC: H01R13/6471 ,  H01R12/73

CPC classification number: H01R13/6471 ,  H01R12/737

Abstract: A new connector implemented with connector pins to reduce crosstalk significantly improves memory channel electrical performance for next generation DDR (double data rate) technology. To reduce crosstalk the connector pins include pins with three different pin shapes, including two differently shaped signal pins and a ground pin that combines the shapes of the signal pins. The shaped pins enables them to be positioned in a connector so that each signal pin can have its own independent and separate signal return path on a single ground pin. In this manner, crosstalk can be significantly reduced.

公开(公告)号：US20220122929A1

公开(公告)日：2022-04-21

申请号：US17561892

申请日：2021-12-24

Applicant: Intel Corporation

Inventor： Xiang LI ,  George VERGIS ,  James A. McCALL

IPC: H01L23/66 ,  H01L23/552 ,  H01L23/00

Abstract: An integrated circuit package includes a substrate with traces for high speed communication that are subject to crosstalk. The traces include overlapping pads on different layers of the substrate, which can increase the mutual capacitance of the signal lines, which will offset the mutual inductance. Thus, the overlapping pads can reduce the crosstalk between the signal traces.

公开(公告)号：US20210313743A1

公开(公告)日：2021-10-07

申请号：US17352211

申请日：2021-06-18

Applicant: Intel Corporation

Inventor： Xiang LI ,  George VERGIS

IPC: H01R13/633 ,  H01R13/635 ,  H01R12/73

Abstract: Apparatus
An apparatus is described. The apparatus includes a dual-in line memory module (DIMM) socket having a first latch and a second latch. One of the first latch and the second latch having a feature for a user to apply force to release a DIMM from the DIMM socket. The other of the first latch and the second latch not having a feature for the user to apply force so that one end of the DIMM releases before an opposite end of the DIMM during release of the DIMM from the DIMM socket.

公开(公告)号：US20190043796A1

公开(公告)日：2019-02-07

申请号：US16017710

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： Zhen ZHOU ,  Jun LIAO ,  Xiang LI ,  Kevin STONE ,  Tom DU ,  Tae-Young YANG ,  Ling ZHENG ,  James A. McCALL

IPC: H01L23/498 ,  H01R12/71 ,  H01R12/52 ,  H01R43/20 ,  H01R43/16 ,  H01R12/57

Abstract: An apparatus is described. The apparatus includes an electro-mechanical interface having angled signal interconnects, wherein, the angling of the signal interconnects is to reduce noise coupling between the angled signal interconnects.