公开(公告)号：US20190303511A1

公开(公告)日：2019-10-03

申请号：US16367493

申请日：2019-03-28

Applicant: Imagination Technologies Limited

Inventor： Robert McKemey ,  Sam Elliott ,  Emiliano Morini ,  Max Freiburghaus

IPC: G06F17/50

Abstract: Methods and systems for verifying a hardware design for a component that implements a permutation respecting function. The methods include formally verifying that an instantiation of the hardware design produces the correct result to the function for a subset of the valid input vectors; and formally verifying that an instantiation of the hardware design is permutation respecting for each of one or more input vector permutations (i.e. that the instantiation of the hardware design produces the permutation related outputs for an input vector and the permutation of that input vector) over a set of input vectors. The subset and the input vector permutations are selected so that any valid input vector that is not in the subset can be generated from an input vector in the subset via a combination of the one or more input vector permutations.

公开(公告)号：US12190035B2

公开(公告)日：2025-01-07

申请号：US17501666

申请日：2021-10-14

Applicant: Imagination Technologies Limited

Inventor： Rachel Edmonds ,  Sam Elliott

IPC: G06F30/3323 ,  G06F119/16

Abstract: Methods and systems for verifying a hardware design for an integrated circuit that implements a function that is polynomial of degree k in a sub-function p over a set of values of p, k being an integer greater than or equal to one. The methods include: verifying that an instantiation of the hardware design correctly evaluates the sub-function p; formally verifying that an instantiation of the hardware design implements a function that is polynomial of degree k in p by formally verifying that, for all values of p in the set of values of p, an instantiation of the hardware design has a constant kth difference; and verifying that an instantiation of the hardware design generates an expected output in response to each of at least e different values of p in the set of values of p, wherein e is equal to k when a value of the kth difference is predetermined and e is equal to k+1 when the value of the kth difference is not predetermined.

公开(公告)号：US11995386B2

公开(公告)日：2024-05-28

申请号：US18201070

申请日：2023-05-23

Applicant: Imagination Technologies Limited

Inventor： Sam Elliott

IPC: G06F30/30 ,  G01R31/3183 ,  G06F30/33 ,  G06F30/3323 ,  G06F30/337 ,  G06F30/3308 ,  G06F111/12 ,  G06F115/02 ,  G06F119/16

CPC classification number: G06F30/33 ,  G01R31/318314 ,  G06F30/3323 ,  G06F30/337 ,  G06F30/3308 ,  G06F2111/12 ,  G06F2115/02 ,  G06F2119/16

Abstract: A hardware design for a main data transformation component is verified. The main data transformation component is representable as a hierarchical set of data transformation components which includes (i) leaf data transformation components which do not have children, and (ii) parent data transformation components which comprise one or more child data transformation components. For each of the leaf data transformation components, it is verified that an instantiation of the hardware design for the leaf data transformation component generates an expected output transaction. For each of the parent data transformation components, it is formally verified that an instantiation of an abstracted hardware design generates an expected output transaction in response to each of test input transactions. The abstracted hardware design for the parent data transformation component represents each of the child data transformation components of the parent data transformation component with a corresponding abstracted component that for a specific input transaction to the child data transformation component produces a specific output transaction with a causal deterministic relationship to the specific input transaction.

公开(公告)号：US11847429B2

公开(公告)日：2023-12-19

申请号：US17588671

申请日：2022-01-31

Applicant: Imagination Technologies Limited

Inventor： Sam Elliott ,  Jonas Olof Gunnar Kallen ,  Casper Van Benthem

IPC: G06F7/485 ,  G06F7/24 ,  G06F7/501 ,  H03K19/20

CPC classification number: G06F7/485 ,  G06F7/24 ,  G06F7/501 ,  H03K19/20

Abstract: Adder circuits and associated methods for processing a set of at least three floating-point numbers to be added together include identifying, from among the at least three numbers, at least two numbers that have the same sign—that is, at least two numbers that are both positive or both negative. The identified at least two numbers are added together using one or more same-sign floating-point adders. A same-sign floating-point adder comprises circuitry configured to add together floating-point numbers having the same sign and does not include circuitry configured to add together numbers having different signs.

公开(公告)号：US11657198B2

公开(公告)日：2023-05-23

申请号：US17384599

申请日：2021-07-23

Applicant: Imagination Technologies Limited

Inventor： Sam Elliott

IPC: G06F30/30 ,  G01R31/3183 ,  G06F30/33 ,  G06F30/3323 ,  G06F30/337 ,  G06F119/16 ,  G06F111/12 ,  G06F115/02 ,  G06F30/3308

CPC classification number: G06F30/33 ,  G01R31/318314 ,  G06F30/337 ,  G06F30/3323 ,  G06F30/3308 ,  G06F2111/12 ,  G06F2115/02 ,  G06F2119/16

Abstract: A hardware design for a main data transformation component is verified. The main data transformation component is representable as a hierarchical set of data transformation components which includes (i) a plurality of leaf data transformation components which do not have children, and (ii) one or more parent data transformation components which each comprise one or more child data transformation components. For each of the plurality of leaf data transformation components, it is verified that an instantiation of the hardware design for the leaf data transformation component generates an expected output transaction in response to each of a plurality of test input transactions. For each of the one or more parent data transformation components, it is formally verified, using a formal verification tool, that an instantiation of an abstracted hardware design for the parent data transformation component generates an expected output transaction in response to each of a plurality of test input transactions. The abstracted hardware design for the parent data transformation component represents each of the one or more child data transformation components of the parent data transformation component with a corresponding abstracted component that for a specific input transaction to the child data transformation component is configured to produce a specific output transaction with a causal deterministic relationship to the specific input transaction.

公开(公告)号：US11609741B2

公开(公告)日：2023-03-21

申请号：US16932923

申请日：2020-07-20

Applicant: Imagination Technologies Limited

Inventor： Sam Elliott

IPC: G06F7/485

Abstract: Circuits and associated methods for processing two floating-point numbers (A, B) to generate a sum (A+B) of the two numbers and a difference (A-B) of the two numbers include calculating (806) a sum (|A|+|B|) of the absolute values of the two floating-point numbers, using a same-sign floating-point adder (1020), to produce a first result. The method further comprises calculating (808) a difference (|A|−|B|) of the absolute values to produce a second result. The sum (A+B) and the difference (A-B) are generated (810, 812) based on the first result (|A|+|B|), the second result (|A|−|B|), and the sign of each floating-point number.

公开(公告)号：US20230030495A1

公开(公告)日：2023-02-02

申请号：US17853694

申请日：2022-06-29

Applicant: Imagination Technologies Limited

Inventor： Thomas Rose ,  Sam Elliott

IPC: G06F7/52

Abstract: A fixed logic circuit configured to perform a multiplication operation a*x, where a is an integer constant, x is an integer variable in the range 0 to 2m−1, and m is a positive integer. The fixed logic circuit includes division logic configured to determine a predetermined number of one or more most significant bits of the result of the division operation: └2ix/q┘ where q,i are selected such that: a*x=└2ix/q┘ Multiplication logic determines a predetermined number of one or more least significant bits of the result of the multiplication operation a*x; and output logic combines the predetermined number of one or more most significant bits of the result of the division operation with the predetermined number of one or more least significant bits of the result of the multiplication operation so as to provide an output for the multiplication operation a*x.

公开(公告)号：US11531800B2

公开(公告)日：2022-12-20

申请号：US17501219

申请日：2021-10-14

Applicant: Imagination Technologies Limited

Inventor： Sam Elliott ,  Rachel Edmonds

IPC: G06F30/3323 ,  G06F30/392 ,  G06F111/04

Abstract: Methods and systems for verifying a hardware design for a component that evaluates a main algebraic expression comprising at least two variables wherein the main algebraic expression is representable as a lossless combination of a plurality of sub-algebraic expressions, and one or more of the at least two variables can be constrained to cause an instantiation of the hardware design to evaluate each of the sub-algebraic expressions. The methods include: for each of the plurality of sub-algebraic expressions, verifying that an instantiation of the hardware design generates a correct output to that sub-algebraic expression for valid values of each variable in that sub-algebraic expression; and for each of one or more combinations of sub-algebraic expressions, formally verifying that an instantiation of the hardware design generates a correct output to that combination by comparing an output of an instantiation of the hardware design under a first set of constraints to an output of an instantiation of the hardware design under a second set of constraints; wherein the one or more combinations comprises a combination that is equivalent to the main algebraic expression.

公开(公告)号：US11455451B2

公开(公告)日：2022-09-27

申请号：US16367493

申请日：2019-03-28

Applicant: Imagination Technologies Limited

Inventor： Robert McKemey ,  Sam Elliott ,  Emiliano Morini ,  Max Freiburghaus

IPC: G06F30/3323 ,  G06F30/33 ,  G06F119/18

Abstract: Methods and systems for verifying a hardware design for a component that implements a permutation respecting function. The methods include formally verifying that an instantiation of the hardware design produces the correct result to the function for a subset of the valid input vectors; and formally verifying that an instantiation of the hardware design is permutation respecting for each of one or more input vector permutations (i.e. that the instantiation of the hardware design produces the permutation related outputs for an input vector and the permutation of that input vector) over a set of input vectors. The subset and the input vector permutations are selected so that any valid input vector that is not in the subset can be generated from an input vector in the subset via a combination of the one or more input vector permutations.

公开(公告)号：US20220114315A1

公开(公告)日：2022-04-14

申请号：US17501219

申请日：2021-10-14

Applicant: Imagination Technologies Limited

Inventor： Sam Elliott ,  Rachel Edmonds

IPC: G06F30/3323

Abstract: Methods and systems for verifying a hardware design for a component that evaluates a main algebraic expression comprising at least two variables wherein the main algebraic expression is representable as a lossless combination of a plurality of sub-algebraic expressions, and one or more of the at least two variables can be constrained to cause an instantiation of the hardware design to evaluate each of the sub-algebraic expressions. The methods include: for each of the plurality of sub-algebraic expressions, verifying that an instantiation of the hardware design generates a correct output to that sub-algebraic expression for valid values of each variable in that sub-algebraic expression; and for each of one or more combinations of sub-algebraic expressions, formally verifying that an instantiation of the hardware design generates a correct output to that combination by comparing an output of an instantiation of the hardware design under a first set of constraints to an output of an instantiation of the hardware design under a second set of constraints; wherein the one or more combinations comprises a combination that is equivalent to the main algebraic expression.