Method and device for radar applications

    公开(公告)号:US10254385B2

    公开(公告)日:2019-04-09

    申请号:US15052099

    申请日:2016-02-24

    Abstract: A device for radar applications includes a computing engine, a radar acquisition unit connected to the computing engine, a timer unit connected to the computing engine, a cascade input port, and a cascade output port. The cascade input port is configured to convey an input signal to the computing engine and the cascade output port is configured to convey an output signal from the computing engine. Further, an according system, a radar system, a vehicle with such radar system and a method are provided.

    METHOD AND DEVICE FOR PROCESSING RADAR SIGNALS
    44.
    发明申请
    METHOD AND DEVICE FOR PROCESSING RADAR SIGNALS 审中-公开
    用于处理雷达信号的方法和装置

    公开(公告)号:US20160282458A1

    公开(公告)日:2016-09-29

    申请号:US15081404

    申请日:2016-03-25

    CPC classification number: G01S13/343 G01S13/931 G01S2007/356 G06F13/28

    Abstract: A device for processing radar signals is suggested, said device comprising a DMA engine, a buffer and a processing stage, wherein the DMA engine is arranged for conducting a read access to a memory, wherein such read access comprises at least two data entries, and for filling the buffer by resorting the at least two data entries, wherein the processing stage is arranged for processing the data stored in the buffer.

    Abstract translation: 提出了一种用于处理雷达信号的装置,所述装置包括DMA引擎,缓冲器和处理级,其中DMA引擎被安排用于对存储器进行读取访问,其中这种读取访问包括至少两个数据条目,以及 用于通过借助所述至少两个数据条目填充所述缓冲器,其中所述处理级被布置用于处理存储在所述缓冲器中的数据。

    Method to enable the prevention of cache thrashing on memory management unit (MMU)-less hypervisor systems

    公开(公告)号:US11232034B2

    公开(公告)日:2022-01-25

    申请号:US16585507

    申请日:2019-09-27

    Abstract: A cache circuit associated with a hypervisor system is disclosed. The cache circuit comprises a cache memory circuit comprising a plurality of cachelines, wherein each cacheline is configured to store data associated with one or more virtual machines (VMs) of a plurality of VMs associated with the hypervisor system and a plurality of tag array entries respectively associated with the plurality of cachelines. In some embodiments, each tag array entry of the plurality of tag entries comprises a tag field configured to store a tag identifier (ID) that identifies an address of a main memory circuit to which a data stored in the corresponding cacheline is associated and a VM tag field configured to store a VM ID associated with a VM to which the data stored in the corresponding cacheline is associated.

    PROCESSING RADAR SIGNALS
    48.
    发明申请

    公开(公告)号:US20210263706A1

    公开(公告)日:2021-08-26

    申请号:US17179886

    申请日:2021-02-19

    Abstract: A radar device is configured to: select a set of operands comprising several operands, determine a common exponent for the operands of the set of operands, normalize the operands based on the common exponent, compress each operand by reducing the resolution of its mantissa, and store the common exponent and the compressed operands in a memory. Also, a vehicle including such radar device and an according method as well as computer program product are provided.

    Radar signal processing
    50.
    发明授权

    公开(公告)号:US11085994B2

    公开(公告)日:2021-08-10

    申请号:US16159957

    申请日:2018-10-15

    Abstract: A radar device including at least three subcircuits, wherein each subcircuit has a cascade input port and a cascade output port and is chained such that the cascade output port of a first subcircuit is connected to the cascade input port of a subsequent subcircuit, the cascade input port of the last subcircuit of the chain is connected to the cascade output port of its preceding subcircuit, and the cascade output port of the last subcircuit of the chain is connectable to an external device, and wherein the at least three subcircuits are configured to conduct a radar computation in a distributed manner such that intermediate results are conveyed towards the last subcircuit of the chain which is configured to combine these results and supply them towards its cascade output port.

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