公开(公告)号：US20210193616A1

公开(公告)日：2021-06-24

申请号：US17024056

申请日：2020-09-17

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Seok Ling Lim ,  Jenny Shio Yin Ong ,  Jackson Chung Peng Kong ,  Kooi Chi Ooi

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/66

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a semiconductor article having a package substrate, a first semiconductor die coupled to the package substrate, a second semiconductor die coupled to the package substrate and adjacent the first semiconductor die, and a bridge component therebetween coupling the first semiconductor die to the second semiconductor die. The bridge component can include a bridge substrate, a conductive trace therein, and a passive component coupled to the conductive trace.

公开(公告)号：US20210193567A1

公开(公告)日：2021-06-24

申请号：US17025115

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jenny Shio Yin Ong ,  Seok Ling Lim ,  Kooi Chi Ooi ,  Jackson Chung Peng Kong

IPC: H01L23/522 ,  H01L23/538 ,  H01L23/528 ,  H01G4/12 ,  H01L49/02

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device can include a semiconductor package including a package substrate, a first semiconductor die on the package substrate, a second semiconductor die on the package substrate, a third semiconductor die on the package substrate, and a bridge interconnect at least partially embedded in the package substrate. The bridge interconnect can include a first bridge section coupling the first semiconductor die to the second semiconductor die, a second bridge section coupling the second semiconductor die to the third semiconductor die, and a power-ground section between the first section and the second section, the power-ground section comprising first and second conductive traces coupled to the second semiconductor die.

公开(公告)号：US10978407B2

公开(公告)日：2021-04-13

申请号：US16402522

申请日：2019-05-03

Applicant: Intel Corporation

Inventor： Jackson Chung Peng Kong ,  Bok Eng Cheah ,  Howard L. Heck ,  Seok Ling Lim ,  Jenny Shio Yin Ong

IPC: H01L23/552 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L21/48 ,  H01L25/00 ,  H01L23/16

Abstract: A stiffener includes an integrated cable-header recess that couples a semiconductor package substrate flexible cable. The flexible cable connects to a device on a board without using interconnections that are arrayed through the board. A semiconductive die is coupled to the semiconductor package substrate and flexible cable through the cable-header recess.

公开(公告)号：US10971440B2

公开(公告)日：2021-04-06

申请号：US16326688

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Khang Choong Yong ,  Po Yin Yaw ,  Kok Hou Teh

IPC: H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H01L23/64 ,  H01L23/66

Abstract: Semiconductor package assemblies and semiconductor packages incorporating an impedance-boosting channel between a transmitter die and a receiver die are described. In an example, a semiconductor package includes a package substrate incorporating the impedance-boosting channel having a first arc segment connected to the transmitter die and a second arc segment connected to the receiver die. The arc segments extend around respective vertical axes passing through a transmitter die electrical bump and a receiver die electrical bump, respectively. Accordingly, the arc segments introduce an inductive circuitry to increase signal integrity of an electrical signal sent from the transmitter die to the receiver die.

公开(公告)号：US10943864B2

公开(公告)日：2021-03-09

申请号：US16469100

申请日：2017-11-29

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Min Suet Lim ,  J-Wing Teh ,  Bok Eng Cheah

IPC: H01L23/525 ,  H01L23/48 ,  H01L23/00 ,  H01L25/00 ,  H01L27/02

Abstract: A device and method of utilizing a programmable redistribution die to redistribute the outputs of semiconductor dies. Integrated circuit packages using a programmable redistribution die are shown. Methods of creating a programmable redistribution die are shown.

公开(公告)号：US20210028094A1

公开(公告)日：2021-01-28

申请号：US17069421

申请日：2020-10-13

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Min Suet Lim ,  Tin Poay Chuah

IPC: H01L23/498 ,  H05K1/18 ,  H05K1/14 ,  H05K3/36 ,  H01L23/538 ,  H05K3/46

Abstract: To address the issue of shrinking volume that can be allocated for electrical components, a system can use an interposer with a flexible portion. A first portion of the interposer can electrically connect to a top side of a motherboard. A flexible portion of the interposer, adjacent to the first portion, can wrap around an edge of the motherboard. A peripheral portion of the interposer, adjacent to the flexible portion, can electrically connect to a bottom side of the motherboard. The peripheral portion can be flexible or rigid. The interposer can define a cavity that extends through the first portion of the interposer. A chip package can electrically connect to the first portion of the interposer. The chip package can be coupled to at least one electrical component that extends into the cavity when the chip package is connected to the interposer.

公开(公告)号：US10652999B2

公开(公告)日：2020-05-12

申请号：US16327453

申请日：2016-10-01

Applicant: Intel Corporation

Inventor： Khang Choong Yong ,  Jackson Chung Peng Kong ,  Bok Eng Cheah ,  Stephen H. Hall

IPC: H05K1/02

Abstract: Embodiments are generally directed to a mutual inductance suppressor for crosstalk immunity enhancement. An embodiment of a printed circuit board includes a first signal trace and a second signal trace on a first layer, wherein the first signal trace and second signal trace are non-intersecting; a second layer below the first layer, the second layer including a voltage reference plane; and a mutual inductance suppressor in the voltage reference plane, the mutual inductance suppressor including a serpentine portion of the voltage reference plane between the first signal trace and the second signal trace.

公开(公告)号：US20200137886A1

公开(公告)日：2020-04-30

申请号：US16565639

申请日：2019-09-10

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Eng Huat Goh ,  Jackson Chung Peng Kong ,  Khang Choong Yong ,  Min Suet Lim

IPC: H05K1/03 ,  H05K1/11 ,  H05K3/46 ,  H05K3/40

Abstract: To overcome the problem of the fiber weave effect desynchronizing differential signals in a pair of traces of approximately the same length in a printed circuit board, the pair of traces can be routed to traverse largely parallel paths that are above one another in the printed circuit board. The material between the paths can include weaved fiber bundles. The material on opposite sides of the paths, surrounding the pair of traces and the weaved fiber bundles, can include resin-rich material. As a result, the pair of traces are directly adjacent to the same materials, which can allow signals in the traces to propagate at the same speed, and prevent desynchronization of differential signals traversing the paths. The path length difference associated with traversing to different depths can be compensated with a relatively small in-plane diagonal jog of one of the traces.

公开(公告)号：US10606316B2

公开(公告)日：2020-03-31

申请号：US15778383

申请日：2015-12-10

Applicant: Intel Corporation

Inventor： Jackson Chung Peng Kong ,  Kooi Chi Ooi ,  Bok Eng Cheah ,  Eng Huat Goh

IPC: G06F1/16 ,  H05K1/02 ,  H05K1/03 ,  H05K1/18 ,  H05K3/00 ,  H05K3/28

Abstract: A flexible electronic device that includes a flexible substrate having an upper surface and a lower surface and interconnects extending between the upper surface and the lower surface; a flexible display mounted directly to the upper surface of the flexible substrate such that the flexible display is electrically connected to the flexible substrate; a first encapsulant mounted to the upper surface of the flexible substrate such that the flexible display is at least partially embedded within the first encapsulant; an electronic component mounted to a lower surface of the flexible substrate such that the electronic component is electrically connected to the flexible substrate; a second encapsulant mounted to the lower surface of the flexible substrate such that the electronic component is at least partially embedded within the second encapsulant; a flexible casing that surrounds the electronic component and the second encapsulant.

公开(公告)号：US20200084880A1

公开(公告)日：2020-03-12

申请号：US16469105

申请日：2017-11-22

Applicant: Intel Corporation

Inventor： Ping Ping Ooi ,  Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Kool Chi Ooi

IPC: H05K1/02 ,  H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H01L25/065

Abstract: A multi-conductor interconnect for a microelectronic device incorporates multiple conductors and integrated shielding for the conductors. The multi-conductor interconnect includes first and second groups of conductors interleaved with one another within a dielectric structure. One of the groups of conductors may be coupled to a reference voltage node to provide shielding for the other group of conductors. The multi-conductor interconnect may further include a shield layer extending over some portion, or all, of the conductors of the first and second groups.