公开(公告)号：US11639556B2

公开(公告)日：2023-05-02

申请号：US15857362

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： Joe Walczyk ,  Pooya Tadayon ,  Andrew Hoitink ,  Tanner Schulz

IPC: C25D17/00 ,  C25D5/02 ,  H05K13/00 ,  H05K3/18 ,  C25D1/00

Abstract: A micronozzle assembly, comprising a reservoir, an array of structures comprising micronozzles, a porous structure positioned between the reservoir and the array, and an electrode within the reservoir, wherein the electrode comprises any of a mesh, a frame along the perimeter of the cavity of the reservoir, or a rod extending into a cavity of the reservoir.

公开(公告)号：US11622466B2

公开(公告)日：2023-04-04

申请号：US16902048

申请日：2020-06-15

Applicant: Intel Corporation

Inventor： Karumbu Meyyappan ,  Kyle Arrington ,  David Craig ,  Pooya Tadayon

IPC: H01L23/498 ,  H05K7/14 ,  H05K7/20 ,  H01L23/22

Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate having a first surface and a second surface opposite from the first surface, and a die on the first surface of the package substrate. In an embodiment, the electronic package further comprises a socket interface on the second surface of the package substrate. In an embodiment, the socket interface comprises a first layer, wherein the first layer comprises a plurality of wells, a liquid metal within the plurality of wells, and a second layer over the plurality of wells.

公开(公告)号：US20230077633A1

公开(公告)日：2023-03-16

申请号：US17476080

申请日：2021-09-15

Applicant: Intel Corporation

Inventor： Changhua Liu ,  Pooya Tadayon ,  John Heck ,  Eric J. Moret ,  Tarek A. Ibrahim ,  Zhichao Zhang ,  Jeremy D Ecton

IPC: G02B6/42

Abstract: An electronic device comprises a photonic integrated circuit (PIC) including at least one waveguide, an emitting lens disposed on the PIC to emit light from the at least one waveguide in a direction substantially parallel to a first surface of the PIC, and an optical element disposed on the PIC and having a reflective surface configured to direct light emitted from the emitting lens in a direction away from the first surface of the PIC.

公开(公告)号：US11581237B2

公开(公告)日：2023-02-14

申请号：US16012126

申请日：2018-06-19

Applicant: Intel Corporation

Inventor： Joe F. Walczyk ,  Pooya Tadayon

IPC: H01L23/367 ,  H01L21/48 ,  H01L23/46 ,  H01L23/373

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a surface; a die having a first surface and an opposing second surface, wherein the first surface of the die is coupled to the surface of the package substrate; and a cooling apparatus that may include a conductive base having a first surface and an opposing second surface, wherein the first surface of the conductive base is in thermal contact with the second surface of the die, and a plurality of conductive structures on the second surface of the conductive base, wherein an individual conductive structure of the plurality of conductive structures has a width between 10 microns and 100 microns.

公开(公告)号：US20220413214A1

公开(公告)日：2022-12-29

申请号：US17359183

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Changhua Liu ,  Pooya Tadayon ,  Zhichao Zhang ,  Liang Zhang ,  Srikant Nekkanty

IPC: G02B6/12 ,  G02B3/06

Abstract: Techniques and mechanisms for facilitating horizontal communication with a photonic integrated circuit (PIC) chip, and a lens structure which is optically coupled thereto. In an embodiment, a PIC chip comprises integrated circuitry, photonic waveguides, and integrated edge-oriented couplers (IECs) which are coupled to the integrated circuitry via the photonic waveguides. The PIC chip forms respective first divergent lens surfaces of the IECs, which are each at a respective terminus of a corresponding one of the photonic waveguides. A lens structure, which is adjacent to the IECs, comprises a second divergent lens surface having an orientation which is substantially orthogonal to the respective orientations of the first divergent lens surfaces. In another embodiment, an edge of the PIC chip forms one or more recess structures, and the lens structure comprises one or more tenon portions which each extends into a respective recess structure of the one or more recess structures.

公开(公告)号：US20220407254A1

公开(公告)日：2022-12-22

申请号：US17352103

申请日：2021-06-18

Applicant: Intel Corporation

Inventor： Zhichao Zhang ,  Zhe Chen ,  Steven A. Klein ,  Feifei Cheng ,  Srikant Nekkanty ,  Kemal Aygun ,  Michael E. Ryan ,  Pooya Tadayon

IPC: H01R12/72 ,  H01R43/16 ,  H01R13/17

Abstract: A microelectronic socket structure and a method of forming the same. The socket structure comprises: a socket structure housing defining a cavity therein; and an interconnection structure including: a contact element disposed at least in part within the cavity, and configured to be electrically coupled to a corresponding microelectronic package, the contact element corresponding to one of a signal contact element or a ground contact element; and a conductive structure disposed at least in part within the cavity, electrically coupled to the contact element, and having an outer contour that is non-conformal with respect to an outer contour of the contact element.

公开(公告)号：US20220375865A1

公开(公告)日：2022-11-24

申请号：US17323253

申请日：2021-05-18

Applicant: Intel Corporation

Inventor： Srinivas V. Pietambaram ,  Krishna Bharath ,  Sai Vadlamani ,  Pooya Tadayon ,  Tarek A. Ibrahim

IPC: H01L23/538 ,  H01L49/02 ,  H01L23/64 ,  H01L25/065

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a glass substrate having a plurality of conductive through-glass vias (TGV); a magnetic core inductor including: a first conductive TGV at least partially surrounded by a magnetic material; and a second conductive TGV electrically coupled to the first TGV; a first die in a first dielectric layer, wherein the first dielectric layer is on the glass substrate; and a second die in a second dielectric layer, wherein the second dielectric layer is on the first dielectric layer, and wherein the second die is electrically coupled to the magnetic core inductor.

公开(公告)号：US20220285079A1

公开(公告)日：2022-09-08

申请号：US17192187

申请日：2021-03-04

Applicant: Intel Corporation

Inventor： Srinivas Pietambaram ,  Pooya Tadayon ,  Kristof Darmawikarta ,  Tarek Ibrahim ,  Prithwish Chatterjee

IPC: H01F27/28 ,  H01F1/04 ,  H01F27/40 ,  H05K1/16

Abstract: An inductor can be formed in a coreless electronic substrate from magnetic materials and/or fabrication processes that do not result in the magnetic materials leaching into plating and/or etching solutions/chemistries, and results in a unique inductor structure. This may be achieved by forming the inductors from magnetic ferrites. The formation of the electronic substrates may also include process sequences that prevent exposure of the magnetic ferrites to the plating and/or etching solutions/chemistries.

公开(公告)号：US20210398966A1

公开(公告)日：2021-12-23

申请号：US17462794

申请日：2021-08-31

Applicant: Intel Corporation

Inventor： Robert L. Sankman ,  Pooya Tadayon ,  Weihua Tang ,  Chandra M. Jha ,  Zhimin Wan

IPC: H01L25/18 ,  H01L23/48 ,  H01L23/42 ,  H01L23/00

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a plurality of dies, a logic die coupled to the plurality of dies, and a dummy die thereon. In selected examples, the dummy die is located between the logic die and the plurality of silicon dies. In selected examples, the dummy die is attached to the logic die.

公开(公告)号：US20200096567A1

公开(公告)日：2020-03-26

申请号：US16141422

申请日：2018-09-25

Applicant: Intel Corporation

Inventor： Paul J. Diglio ,  Pooya Tadayon ,  Karumbu Meyyappan

IPC: G01R31/319 ,  G01R1/073

Abstract: Embodiments herein relate to a test probe. The test probe may have a first plurality of beams and a second plurality of beams. An intermediate substrate may be positioned between the first plurality of beams and the second plurality of beams. In embodiments, both the first and second plurality of beams may be angled. Other embodiments may be described or claimed.