公开(公告)号：US11646244B2

公开(公告)日：2023-05-09

申请号：US16454343

申请日：2019-06-27

Applicant: Intel Corporation

Inventor： Steven A. Klein ,  Zhimin Wan ,  Chia-Pin Chiu ,  Shankar Devasenathipathy

IPC: H01L23/40 ,  H01R12/71 ,  H01R13/73 ,  H01L23/427

CPC classification number: H01L23/4006 ,  H01L23/427 ,  H01R12/716 ,  H01R13/73 ,  H01L2023/4062 ,  H01L2023/4087

Abstract: A microprocessor mounting apparatus comprising a microprocessor socket on a printed circuit board (PCB) and a bolster plate surrounding a perimeter of the microprocessor socket. The bolster plate has a first surface adjacent to the PCB, and a second surface opposite the first surface. A heat dissipation device is on the second surface of the bolster plate. The heat dissipation interface is thermally coupled to the microprocessor socket.

公开(公告)号：US20240113479A1

公开(公告)日：2024-04-04

申请号：US17957761

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Kai Xiao ,  Phil Geng ,  Carlos Alberto Lizalde Moreno ,  Raul Enriquez Shibayama ,  Steven A. Klein

IPC: H01R13/6597 ,  H01R12/71 ,  H01R13/50 ,  H01R13/6471 ,  H01R33/74 ,  H01R43/18 ,  H01R43/20

CPC classification number: H01R13/6597 ,  H01R12/714 ,  H01R13/50 ,  H01R13/6471 ,  H01R33/74 ,  H01R43/18 ,  H01R43/20 ,  H01R12/57

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for socket interconnect structures and related methods. An example socket interconnect apparatus includes a housing defining a plurality of first openings and a plurality of second openings and a ground structure coupled to the housing. The ground structure defines a plurality of third openings. The third openings of the ground structure align with the second openings of the housing when the ground structure is coupled to the housing. A plurality of ground pins are located in respective ones of the second openings and third openings. The ground structure is to electrically couple the ground pins. A plurality of signal pins are located in respective ones of the first openings of the housing. The signal pins are electrically isolated from the ground structure.

公开(公告)号：US11916003B2

公开(公告)日：2024-02-27

申请号：US16575307

申请日：2019-09-18

Applicant: Intel Corporation

Inventor： Xiao Lu ,  Jiongxin Lu ,  Christopher Combs ,  Alexander Huettis ,  John Harper ,  Jieping Zhang ,  Nachiket R. Raravikar ,  Pramod Malatkar ,  Steven A. Klein ,  Carl Deppisch ,  Mohit Sood

IPC: H01L23/48 ,  B23K3/06 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L23/49833 ,  B23K3/0623 ,  H01L23/49822 ,  H01L23/4985 ,  H01L23/5387

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first substrate; a second substrate; and an array of interconnects electrically coupling the first substrate to the second substrate. In an embodiment, the array of interconnects comprises first interconnects, wherein the first interconnects have a first volume and a first material composition, and second interconnects, wherein the second interconnects have a second volume and a second material composition, and wherein the first volume is different than the second volume and/or the first material composition is different than the second material composition.

公开(公告)号：US12127363B2

公开(公告)日：2024-10-22

申请号：US17033401

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Feifei Cheng ,  Thomas Boyd ,  Kuang Liu ,  Steven A. Klein ,  Daniel Neumann ,  Mohanraj Prabhugoud

IPC: H05K7/10 ,  H01R12/52

CPC classification number: H05K7/1069 ,  H01R12/523

Abstract: Embodiments disclosed herein include sockets and electronic packages with socket architectures. In an embodiment, a socket comprises a housing with a first surface and a second surface. In an embodiment, a plurality of interconnect pins pass through the housing. In an embodiment, an alignment hole is provided through the housing. In an embodiment, an alignment post extending out from the first surface of the housing is also provided.

公开(公告)号：US20220407254A1

公开(公告)日：2022-12-22

申请号：US17352103

申请日：2021-06-18

Applicant: Intel Corporation

Inventor： Zhichao Zhang ,  Zhe Chen ,  Steven A. Klein ,  Feifei Cheng ,  Srikant Nekkanty ,  Kemal Aygun ,  Michael E. Ryan ,  Pooya Tadayon

IPC: H01R12/72 ,  H01R43/16 ,  H01R13/17

Abstract: A microelectronic socket structure and a method of forming the same. The socket structure comprises: a socket structure housing defining a cavity therein; and an interconnection structure including: a contact element disposed at least in part within the cavity, and configured to be electrically coupled to a corresponding microelectronic package, the contact element corresponding to one of a signal contact element or a ground contact element; and a conductive structure disposed at least in part within the cavity, electrically coupled to the contact element, and having an outer contour that is non-conformal with respect to an outer contour of the contact element.

公开(公告)号：US20180089984A1

公开(公告)日：2018-03-29

申请号：US15277811

申请日：2016-09-27

Applicant: Intel Corporation

Inventor： Vijay Krishnan Subramanian ,  Steven A. Klein ,  Pramod Malatkar ,  Rajendra C. Dias ,  Aleksandar Aleksov ,  Jason P. Glumbik ,  Nadine L. Dabby

IPC: G08B21/18 ,  H05K1/02 ,  H05K1/18 ,  G01R31/28

CPC classification number: G01R31/2846 ,  H05K1/0268 ,  H05K1/189 ,  H05K2201/09263 ,  H05K2201/10151

Abstract: Techniques and mechanisms for determining a level of degradation of flexible circuitry. In an embodiment, a flexible substrate has disposed therein first circuitry and one or more components coupled thereto, the one or more components to monitor a physical property of the first circuitry. Further disposed in or on the flexible substrate are memory resources to store predefined reference information which corresponds amounts of the physical property each with a different respective level of degradation. Evaluation logic accesses the reference information to determine, based on a detected amount of the physical property, a level of degradation of second circuitry. In another embodiment, the second circuitry is more flexible, as compared to the first circuitry.

公开(公告)号：US20240297119A1

公开(公告)日：2024-09-05

申请号：US18573116

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Srikant Nekkanty ,  Karumbu Meyyappan ,  Andres Ramirez Macias ,  Zhe Chen ,  Jeffory L. Smalley ,  Zhichao Zhang ,  Steven A. Klein ,  Eric Erike

IPC: H01L23/532 ,  H01L23/32 ,  H01L23/40 ,  H01L23/498 ,  H01L23/528

CPC classification number: H01L23/53209 ,  H01L23/32 ,  H01L23/4093 ,  H01L23/49811 ,  H01L23/5283

Abstract: An electronic device (100, 800, 1000) and associated methods are disclosed. In one example, the electronic device (100, 800, 1000) includes an interconnect socket (102, 302, 402, 802, 1004, 1320, 1402, 1506) that includes a liquid metal. In selected examples, the interconnect socket (102, 302, 402) includes a resilient material spacer (130, 230, 330, 430) located between pins (110, 210, 310, 410) in an array of pins (110, 210, 310, 410). In selected examples, the electronic device (1000) includes configurations to aid in de-socketing.

公开(公告)号：US11581671B2

公开(公告)日：2023-02-14

申请号：US16361537

申请日：2019-03-22

Applicant: Intel Corporation

Inventor： Zhimin Wan ,  Steven A. Klein ,  Chia-Pin Chiu ,  Shankar Devasenathipathy

IPC: H01R13/62 ,  H01R12/70 ,  H01R13/50 ,  H01R13/24 ,  H01R12/71

Abstract: An integrated circuit (IC) socket comprising a housing with a land side, an opposing die side, and sidewalls around a perimeter of the housing. The housing comprises a first dielectric. A plurality of socket pins extends from the land side of the housing through socket pin holes in the housing over the die side of the housing. A second dielectric is within the interstitial regions between the socket pins and sidewalls of the socket pin holes. A frame structure extends around at least a portion of the perimeter of the housing, and a mesh structure is embedded within the first dielectric. The mesh structure has plurality of mesh filaments extending between the plurality of socket pin holes and coupled to the frame structure.

公开(公告)号：US11569596B2

公开(公告)日：2023-01-31

申请号：US16833221

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Steven A. Klein ,  Kuang Liu ,  Srikant Nekkanty ,  Feroz Mohammad ,  Donald Tiendung Tran ,  Srinivasa Aravamudhan ,  Hemant Mahesh Shah ,  Alexander W. Huettis

IPC: H01R12/00 ,  H01R12/70 ,  H01R43/04

Abstract: Systems, apparatus, and/or processes directed to applying pressure to a socket to alter a shape of the socket to improve a connection between the socket and a substrate, printed circuit board, or other component. The socket may receive one or more chips, may be an interconnect, or may be some other structure that is part of a package. The shape of the socket may be flattened so that a side of the socket may form a high-quality physical and electrical coupling with the substrate.

公开(公告)号：US11818832B2

公开(公告)日：2023-11-14

申请号：US16828447

申请日：2020-03-24

Applicant: Intel Corporation

Inventor： Feroz Mohammad ,  Ralph V. Miele ,  Thomas Boyd ,  Steven A. Klein ,  Gregorio R. Murtagian ,  Eric W. Buddrius ,  Daniel Neumann ,  Rolf Laido

IPC: H05K1/02 ,  H01R12/85 ,  H05K7/20 ,  H01L23/40 ,  H05K1/18

CPC classification number: H05K1/0203 ,  H05K7/20509 ,  H01L2023/405 ,  H01L2023/4087 ,  H01R12/85 ,  H05K1/181 ,  H05K2201/10325

Abstract: Embodiments disclosed herein include assemblies. In an embodiment, an assembly comprises a socket and a bolster plate on a board, where the bolster plate has load studs and an opening that surrounds the socket; a shim having first and second ends; and a carrier on the bolster plate, where the carrier has an opening and cutouts. The shim may have an opening through the first end as the second end is affixed to the carrier. The opening of the shim entirely over one cutout from a corner region of the carrier. In an embodiment, the assembly comprises an electronic package in the opening of the carrier, where the electronic package is affixed to the carrier, and a heatsink over the electronic package and carrier, where the first end is directly coupled to a surface of the heatsink and a surface of one load stud of the bolster plate.