公开(公告)号：US08819394B2

公开(公告)日：2014-08-26

申请号：US13721725

申请日：2012-12-20

Applicant: Intel Corporation

Inventor： Michael A. Julier ,  Jeffrey D. Gray ,  Srinivas Chennupaty ,  Sean P. Mirkes ,  Mark P. Seconi

IPC: G06F7/06 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30145 ,  G06F7/06 ,  G06F9/30 ,  G06F9/3001 ,  G06F9/30021 ,  G06F9/30029 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/30185 ,  G06F9/30192 ,  G06F9/34 ,  G06F9/3802 ,  G06F9/3824 ,  G06F9/3853 ,  G06F9/3885 ,  G06F9/3887 ,  G06F12/0875 ,  G06F2212/452

Abstract: Methods, apparatus, and instructions for performing string comparison operations. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store a result of a comparison between each data element of a first and second operand corresponding to a first and second text string, respectively.

Abstract translation: 用于执行字符串比较操作的方法，装置和指令。 在一个实施例中，一种装置包括执行第一指令的执行资源。 响应于第一指令，所述执行资源分别存储对应于第一和第二文本串的第一和第二操作数的每个数据元素之间的比较结果。

公开(公告)号：US11029955B2

公开(公告)日：2021-06-08

申请号：US16458014

申请日：2019-06-29

Applicant: Intel Corporation

Inventor： Michael A. Julier ,  Jeffrey D. Gray ,  Srinivas Chennupaty ,  Sean P. Mirkes ,  Mark P. Seconi

IPC: G06F9/30 ,  G06F9/38 ,  G06F7/06 ,  G06F12/0875 ,  G06F9/34

Abstract: Method, apparatus, and program means for performing a string comparison operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store a result of a comparison between each data element of a first and second operand corresponding to a first and second text string, respectively.

公开(公告)号：US10581590B2

公开(公告)日：2020-03-03

申请号：US14984637

申请日：2015-12-30

Applicant: Intel Corporation

Inventor： Shay Gueron ,  Wajdi K Feghali ,  Vinodh Gopal ,  Raghunandan Makaram ,  Martin G Dixon ,  Srinivas Chennupaty ,  Michael E Kounavis

IPC: H04L9/28 ,  G06F21/72 ,  H04L9/06 ,  G06F9/30 ,  G06F9/38 ,  H04L9/08 ,  G06F12/14 ,  G06F21/60 ,  G06F12/0875 ,  G06F12/0862 ,  G11C7/10 ,  G06F3/06

Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.

公开(公告)号：US10164769B2

公开(公告)日：2018-12-25

申请号：US14984588

申请日：2015-12-30

Applicant: Intel Corporation

Inventor： Shay Gueron ,  Wajdi K Feghali ,  Vinodh Gopal ,  Raghunandan Makaram ,  Martin G Dixon ,  Srinivas Chennupaty ,  Michael E Kounavis

IPC: H04L9/28 ,  G06F21/72 ,  H04L9/06 ,  H04L9/08 ,  G06F12/14 ,  G06F21/60 ,  G06F12/0875 ,  G06F9/30 ,  G06F12/0862 ,  G06F9/38 ,  G11C7/10 ,  G06F3/06

Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.

公开(公告)号：US20180052689A1

公开(公告)日：2018-02-22

申请号：US15797524

申请日：2017-10-30

Applicant: Intel Corporation

Inventor： Michael A. Julier ,  Jeffrey D. Gray ,  Srinivas Chennupaty ,  Sean P. Mirkes ,  Mark P. Seconi

IPC: G06F9/30 ,  G06F7/06 ,  G06F9/38 ,  G06F9/34

CPC classification number: G06F9/30145 ,  G06F7/06 ,  G06F9/30 ,  G06F9/3001 ,  G06F9/30021 ,  G06F9/30029 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/30185 ,  G06F9/30192 ,  G06F9/34 ,  G06F9/3802 ,  G06F9/3824 ,  G06F9/3853 ,  G06F9/3885 ,  G06F9/3887 ,  G06F12/0875 ,  G06F2212/452

Abstract: Method, apparatus, and program means for performing a string comparison operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store a result of a comparison between each data element of a first and second operand corresponding to a first and second text string, respectively.

公开(公告)号：US09703564B2

公开(公告)日：2017-07-11

申请号：US14576124

申请日：2014-12-18

Applicant: Intel Corporation

Inventor： Michael A. Julier ,  Jeffrey D. Gray ,  Srinivas Chennupaty ,  Sean P. Mirkes ,  Mark P. Seconi

IPC: G06F9/30 ,  G06F9/38 ,  G06F7/06 ,  G06F12/0875 ,  G06F9/34

CPC classification number: G06F9/30145 ,  G06F7/06 ,  G06F9/30 ,  G06F9/3001 ,  G06F9/30021 ,  G06F9/30029 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/30185 ,  G06F9/30192 ,  G06F9/34 ,  G06F9/3802 ,  G06F9/3824 ,  G06F9/3853 ,  G06F9/3885 ,  G06F9/3887 ,  G06F12/0875 ,  G06F2212/452

Abstract: A processor to perform a string comparison instruction. The processor includes a decoder to decode the string comparison instruction. The packed comparison instruction is to have an immediate that is to be used to control performance of the string comparison instruction. The immediate includes a first set of two bits, a second set of two bits, a third set of two bits, and a fourth bit. The processor also includes an execution unit coupled with the decoder to execute the packed comparison instruction.

公开(公告)号：US09634830B2

公开(公告)日：2017-04-25

申请号：US14572620

申请日：2014-12-16

Applicant: Intel Corporation

Inventor： Shay Gueron ,  Wajdi K. Feghali ,  Vinodh Gopal ,  Raghunandan Makaram ,  Martin G. Dixon ,  Srinivas Chennupaty ,  Michael E. Kounavis

IPC: H04L9/06 ,  H04L9/28 ,  H04L9/08 ,  G06F12/14 ,  G06F21/60 ,  G06F12/0875 ,  G06F9/30 ,  G06F12/0862 ,  G06F9/38 ,  G11C7/10 ,  G06F3/06

CPC classification number: H04L9/0631 ,  G06F3/0623 ,  G06F3/0665 ,  G06F3/0689 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/30047 ,  G06F9/30145 ,  G06F9/30178 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3887 ,  G06F9/3895 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1408 ,  G06F21/602 ,  G06F2212/1052 ,  G06F2212/402 ,  G06F2212/452 ,  G06F2212/454 ,  G06F2212/602 ,  G11C7/1072 ,  H04L9/0816 ,  H04L9/0861 ,  H04L2209/12 ,  H04L2209/24

Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.

公开(公告)号：US20160196219A1

公开(公告)日：2016-07-07

申请号：US14872584

申请日：2015-10-01

Applicant: Intel Corporation

Inventor： Shay Gueron ,  Wajdi K. Feghali ,  Vinodh Gopal ,  Raghunandan Makaram ,  Martin G. Dixon ,  Srinivas Chennupaty ,  Michael Kounavis

IPC: G06F12/14 ,  G06F9/30 ,  G06F9/38 ,  G06F12/08

CPC classification number: H04L9/0631 ,  G06F3/0623 ,  G06F3/0665 ,  G06F3/0689 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/30047 ,  G06F9/30145 ,  G06F9/30178 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3887 ,  G06F9/3895 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1408 ,  G06F21/602 ,  G06F2212/1052 ,  G06F2212/402 ,  G06F2212/452 ,  G06F2212/454 ,  G06F2212/602 ,  G11C7/1072 ,  H04L9/0816 ,  H04L9/0861 ,  H04L2209/12 ,  H04L2209/24

Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.

公开(公告)号：US20160119129A1

公开(公告)日：2016-04-28

申请号：US14984663

申请日：2015-12-30

Applicant: Intel Corporation

Inventor： Gueron Shay ,  Wajdi K. Feghali ,  Vinodh Gopal ,  Raghunandan Makaram ,  Martin G. Dixon ,  Srinivas Chennupaty ,  Michael E. Kounavis

IPC: H04L9/06 ,  G06F12/08

CPC classification number: H04L9/0631 ,  G06F3/0623 ,  G06F3/0665 ,  G06F3/0689 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/30047 ,  G06F9/30145 ,  G06F9/30178 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3887 ,  G06F9/3895 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1408 ,  G06F21/602 ,  G06F2212/1052 ,  G06F2212/402 ,  G06F2212/452 ,  G06F2212/454 ,  G06F2212/602 ,  G11C7/1072 ,  H04L9/0816 ,  H04L9/0861 ,  H04L2209/12 ,  H04L2209/24

Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.

公开(公告)号：US20160119127A1

公开(公告)日：2016-04-28

申请号：US14984647

申请日：2015-12-30

Applicant: Intel Corporation

Inventor： Gueron Shay ,  Wajdi K. Feghali ,  Vinodh Gopal ,  Raghunandan Makaram ,  Martin G. Dixon ,  Srinivas Chennupaty ,  Michael E. Kounavis

IPC: H04L9/06 ,  G06F9/38 ,  G06F21/60

CPC classification number: H04L9/0631 ,  G06F3/0623 ,  G06F3/0665 ,  G06F3/0689 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/30047 ,  G06F9/30145 ,  G06F9/30178 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3887 ,  G06F9/3895 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1408 ,  G06F21/602 ,  G06F2212/1052 ,  G06F2212/402 ,  G06F2212/452 ,  G06F2212/454 ,  G06F2212/602 ,  G11C7/1072 ,  H04L9/0816 ,  H04L9/0861 ,  H04L2209/12 ,  H04L2209/24

Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.