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286 条记录 (耗时 0.028 秒)

    FULLY-ALIGNED SKIP-VIAS
    42.
    发明申请
    FULLY-ALIGNED SKIP-VIAS 有权

    公开(公告)号：US20210225760A1

    公开(公告)日：2021-07-22

    申请号：US16748951

    申请日：2020-01-22

    申请人： International Business Machines Corporation

    发明人： Kenneth Chun Kuen Cheng ,  Chanro Park ,  Koichi Motoyama ,  Chih-Chao Yang

    IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L23/528

    摘要： An interconnect structure includes a first electrically conductive via portion on an upper surface of a substrate, the first electrically conductive via elongated along a first direction, and a first ILD material on the substrate and covering the first electrically conductive via portion. The first ILD material includes an ILD upper surface exposing a via surface of the first electrically conductive via portion. A second electrically conductive via portion is on the ILD upper surface and the via upper surface thereby defining a contact area between the first electrically conductive via portion and the second electrically conductive via portion. The second electrically conductive via portion elongated along a second direction orthogonal with respect to the first direction. A second ILD material is on the ILD upper surface to cover the second electrically conductive via portion. The first and second electrically conductive via portions are fully aligned at the contact area.

    Gate cap last for self-aligned contact
    43.
    发明授权
    Gate cap last for self-aligned contact 有权

    公开(公告)号：US11031295B2

    公开(公告)日：2021-06-08

    申请号：US16429371

    申请日：2019-06-03

    申请人： International Business Machines Corporation

    发明人： Chanro Park ,  Kangguo Cheng ,  Ruilong Xie ,  Choonghyun Lee

    IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L21/768 ,  H01L29/78 ,  H01L21/311 ,  H01L29/66

    摘要： Embodiments of the present invention are directed to a gate cap last process for forming a self-aligned contact. This gate cap last process allows for a thin SAC cap, as the SAC cap only needs to prevent a short between the metallization contact and the gate. In a non-limiting embodiment of the invention, a gate is formed over a channel region of a fin. The gate can include a gate spacer. A sacrificial contact is formed on a top surface of a source or drain (S/D) region of a substrate. The sacrificial contact is positioned directly adjacent to a sidewall of the gate spacer. An exposed surface of the gate is recessed to form a recessed gate surface and a self-aligned contact (SAC) cap is formed on the recessed gate surface. The sacrificial contact is replaced with a S/D contact.

    SEMICONDUCTOR DEVICE WITH IMPROVED CONTACT RESISTANCE AND VIA CONNECTIVITY
    44.
    发明申请
    SEMICONDUCTOR DEVICE WITH IMPROVED CONTACT RESISTANCE AND VIA CONNECTIVITY 有权

    公开(公告)号：US20210151323A1

    公开(公告)日：2021-05-20

    申请号：US17133178

    申请日：2020-12-23

    申请人： International Business Machines Corporation

    发明人： Chanro Park ,  Kangguo Cheng ,  Ruilong Xie ,  Juntao Li

    IPC分类号： H01L21/285 ,  H01L29/66 ,  H01L29/78 ,  H01L29/45

    摘要： A method is provided which includes forming a semiconductor substrate having one or more fins. The method includes forming over the fins a plurality of gate structures. The method includes forming gate spacers on sidewalls of the gate structure. The method includes forming a source/drain region on the semiconductor substrate between each adjacent gate spacer. The method includes depositing an interlevel dielectric layer on the source/drain regions and over the gate structures. The method includes depositing a hardmask on the interlevel dielectric layer. The method includes patterning the hardmask to form a plurality of openings and exposing the top surface of each of the source/drain regions. The method includes depositing an optical planarization layer in a portion of the openings and above the top surface of the gate structures. The method includes etching the interlevel dielectric layer in the opening to form an undercut region below the hardmask.

    Transistor having airgap spacer around gate structure
    45.
    发明授权
    Transistor having airgap spacer around gate structure 有权

    公开(公告)号：US11011638B2

    公开(公告)日：2021-05-18

    申请号：US16550793

    申请日：2019-08-26

    申请人： International Business Machines Corporation

    发明人： Ruilong Xie ,  Julien Frougier ,  Kangguo Cheng ,  Chanro Park

    IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/41 ,  H01L29/66 ,  H01L29/49 ,  H01L29/417

    摘要： An integrated semiconductor device having a gate structure adjacent to a semiconductor body at a channel region, the channel region being positioned laterally between source/drain regions. Metal plugs are on the source/drain regions, and rectangular-shaped or trapezoidal-shaped plug caps are above and immediately adjacent to the metal plugs. A self-aligned metal filled contact (CA) is conductively coupled to one of the metal plugs on the source and drain regions, and a self-aligned metal filled contact (CBoA) is conductively coupled to the gate structure. The device further includes a low k dielectric layer that includes a continuous airgap having an inverted u-shape formed about the gate structure and breaks at about a portion of the gate structure including the self-aligned metal filled contact (CBoA). Also, methods for forming the device including the uniquely shaped continuous airgap are disclosed.

    Extreme ultraviolet patterning process with resist hardening
    47.
    发明授权
    Extreme ultraviolet patterning process with resist hardening 有权

    公开(公告)号：US10971362B2

    公开(公告)日：2021-04-06

    申请号：US16287107

    申请日：2019-02-27

    申请人： International Business Machines Corporation

    发明人： Chanro Park ,  Ruilong Xie ,  Kangguo Cheng ,  Choonghyun Lee

    IPC分类号： H01L21/033 ,  H01L21/027 ,  G03F7/20 ,  H01L21/308

    摘要： A photolithography patterning stack and method for forming the same. The stack includes a plurality of patterned silicon oxide lines. A plurality of patterned silicon germanium lines each underlie and contact one patterned silicon oxide line of the plurality of patterned silicon oxide lines. The photolithography patterning stack further comprises a plurality of layers underlying the plurality of patterning silicon germanium lines. The method includes patterning at least a photoresist layer of a photolithographic patterning stack. The patterning exposing portions of a silicon germanium layer of the photolithographic patterning stack. A germanium oxide layer is formed in contact with the patterned photoresist layer and the portions of the silicon germanium layer. A plurality of silicon oxide layers is formed from the germanium oxide layer. Each of the silicon oxide layer is in contact with one of the portions of the silicon germanium layer.

    VERTICAL TRANSISTOR WITH SELF-ALIGNED GATE
    48.
    发明申请
    VERTICAL TRANSISTOR WITH SELF-ALIGNED GATE 有权

    公开(公告)号：US20210057565A1

    公开(公告)日：2021-02-25

    申请号：US16546479

    申请日：2019-08-21

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Juntao Li ,  Kangguo Cheng ,  Ruilong Xie ,  Chanro Park

    IPC分类号： H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8238

    摘要： A method of forming a vertical transistor is provided. The method includes forming a first set of vertical fins in a first row on a first bottom source/drain layer, and a second set of vertical fins in a second row on a second bottom source/drain layer, wherein the vertical fins in the same row are separated by a spacing with a sidewall-to-sidewall distance, SD, and the vertical fins in the same column of adjacent rows are separated by a gap having a gap distance, GD. The method further includes forming a gate metal layer on the first set of vertical fins and the second set of vertical fins, wherein the gate metal layer does not fill in the gap between vertical fins in the same column, and forming a cover layer plug in the remaining gap after forming the gate metal layer.

    Airgap vertical transistor without structural collapse
    49.
    发明授权
    Airgap vertical transistor without structural collapse 有权

    公开(公告)号：US10896845B2

    公开(公告)日：2021-01-19

    申请号：US16439880

    申请日：2019-06-13

    申请人： International Business Machines Corporation

    发明人： Kangguo Cheng ,  Chanro Park ,  Juntao Li ,  Ruilong Xie

    IPC分类号： H01L21/768 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L21/764 ,  H01L21/762 ,  H01L21/311 ,  H01L21/8234 ,  H01L21/8238

    摘要： Embodiments of the present invention are directed to forming an airgap-based vertical field effect transistor (VFET) without structural collapse. A dielectric collar anchors the structure while forming the airgaps. In a non-limiting embodiment of the invention, a vertical transistor is formed over a substrate. The vertical transistor can include a fin, a top spacer, a top source/drain (S/D) on the fin, and a contact on the top S/D. A dielectric layer is recessed below a top surface of the top spacer and a dielectric collar is formed on the recessed surface of the dielectric layer. Portions of the dielectric layer are removed to form a first cavity and a second cavity. A first airgap is formed in the first cavity and a second airgap is formed in the second cavity. The dielectric collar anchors the top S/D to the top spacer while forming the first airgap and the second airgap.