公开(公告)号：US20250072116A1

公开(公告)日：2025-02-27

申请号：US18452682

申请日：2023-08-21

Applicant: International Business Machines Corporation

Inventor： Juntao Li ,  Ruilong Xie ,  Julien Frougier ,  Min Gyu Sung ,  Chanro Park

IPC: H01L27/12 ,  H01L21/8234 ,  H01L21/84

Abstract: A semiconductor device comprises a first nanosheet transistor disposed on a semiconductor substrate, the first nanosheet transistor comprising a plurality of first gate structures, and a second nanosheet transistor disposed on the semiconductor substrate, the second nanosheet transistor comprising a plurality of second gate structures. Respective stacked spacer structures are disposed on respective sides of respective ones of the plurality of second gate structures, wherein each of the respective stacked spacer structures comprises a first spacer and a second spacer. Respective ones of the plurality of first gate structures comprise a first nanosheet gate portion and a gate dielectric layer around the first nanosheet gate portion. The respective ones of the plurality of second gate structures comprise a second nanosheet gate portion and at least two gate dielectric layers around the second nanosheet gate portion.

公开(公告)号：US20250008719A1

公开(公告)日：2025-01-02

申请号：US18344838

申请日：2023-06-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Min Gyu Sung ,  Ruilong Xie ,  Julien Frougier ,  Chanro Park ,  Juntao Li ,  Tao Li

IPC: H10B10/00 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device, includes a source and drain bottom epitaxial layer positioned on top of a dielectric substrate. A metal gate is positioned on top of the bottom epitaxial layer. A source and drain top epitaxial layer is positioned on top of the metal gate. A first and second semiconductor channel pass vertically from the source and drain top epitaxial layer through the metal gate to the source and drain bottom epitaxial layer. First and second metal contacts are conductively coupled to the first and second semiconductor channels. First and second metal vias are formed on a backside of the source and drain bottom epitaxial layer and arranged in conductive contact with the first and second semiconductor channels. A metal layer is formed on a backside of the first and second metal vias.

公开(公告)号：US12119346B2

公开(公告)日：2024-10-15

申请号：US17480717

申请日：2021-09-21

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Shogo Mochizuki ,  Juntao Li

IPC: H01L27/08 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L29/0847 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851

Abstract: A vertical field-effect transistor device includes a substrate comprising a semiconductor material, and a set of fins formed from the semiconductor material and extending vertically with respect to the substrate. The vertical field-effect transistor device further includes gate structures disposed on the substrate and on a portion of sidewalls of the set of fins, spacers disposed on the gate structures and on a remaining portion of the sidewalls of the set of fins, source/drain regions disposed over top portions of the set of fins, and a metal liner disposed adjacent and over the source/drain regions such that a wrap-around contact is defined to cover an upper area of the source/drain regions. A portion of the source/drain regions is configured to have a lateral width less than a width between adjacent gate structures on the respective fin.

公开(公告)号：US20240332082A1

公开(公告)日：2024-10-03

申请号：US18191895

申请日：2023-03-29

Applicant: International Business Machines Corporation

Inventor： Min Gyu Sung ,  Ruilong Xie ,  Julien Frougier ,  Chanro Park ,  Juntao Li

IPC: H01L21/822 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/146 ,  H01L29/68

CPC classification number: H01L21/8221 ,  H01L21/823481 ,  H01L27/0225 ,  H01L27/14612 ,  H01L29/685

Abstract: Embodiments of the invention are directed to an integrated circuit (IC) that includes a stacked device configuration having a top electronic device positioned over a bottom electronic device, along with an isolation region operable to electrically isolate at least a gate region of the top electronic device from a gate region of the bottom electronic device. The gate region of the top electronic device includes a first conductive material, and the gate region of the bottom electronic device includes a second conductive material that is different from the first conductive material.

公开(公告)号：US20240215462A1

公开(公告)日：2024-06-27

申请号：US18146344

申请日：2022-12-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ning Li ,  Andrew Herbert Simon ,  Injo Ok ,  Kangguo Cheng ,  Timothy Mathew Philip ,  Kevin W. Brew ,  Jin Ping Han ,  Juntao Li ,  Nicole Saulnier

IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

CPC classification number: H01L45/1253 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/16

Abstract: An electrical device includes a first electrode in series with a second electrode. A phase change memory (PCM) is in series with the second electrode. A variable electrical element is in series with the phase change memory.

公开(公告)号：US20240213248A1

公开(公告)日：2024-06-27

申请号：US18145034

申请日：2022-12-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Julien Frougier ,  Chanro Park ,  Min Gyu Sung ,  Juntao Li

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L23/535 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L27/0922 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/535 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

Abstract: A semiconductor structure including stacked transistor structures each including a top device stacked directly above a bottom device, and a placeholder dielectric and a backside gate contact within a dielectric capping layer beneath the stacked transistor structures, where the placeholder dielectric is directly below a first bottom source drain region, and the backside gate contact is directly below a second bottom source drain region.

公开(公告)号：US20240194677A1

公开(公告)日：2024-06-13

申请号：US18064260

申请日：2022-12-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Min Gyu Sung ,  Julien Frougier ,  Ruilong Xie ,  Chanro Park ,  Juntao Li

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L27/092 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: A semiconductor device includes a first nanosheet field effect transistor (PET) having a first gate stack arranged on a substrate. A second nanosheet FET is arranged on the substrate adjacent to the first nanosheet FET. The second FET includes a second gate stack, wherein a top of the first gate stack and a top of the second gate stack have different heights.

公开(公告)号：US11963469B2

公开(公告)日：2024-04-16

申请号：US18317123

申请日：2023-05-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Ruilong Xie ,  Carl Radens ,  Juntao Li

IPC: H10N70/00 ,  G11C13/00

CPC classification number: H10N70/841 ,  G11C13/0004 ,  H10N70/011 ,  H10N70/8265 ,  H10N70/8825 ,  H10N70/8828

Abstract: A phase change memory (PCM) cell comprising a substrate a first electrode located on the substrate. A phase change material layer located adjacent to the first electrode, wherein a first side of the phase change material layer is in direct contact with the first electrode. A second electrode located adjacent to phase change material layer, wherein the second electrode is in direct contact with a second side of the phase change material layer, wherein the first side and the second side are different sides of the phase change material layer. An airgap is located directly above the phase change material layer, wherein the airgap provides space for the phase change material to expand or restrict.

公开(公告)号：US11937522B2

公开(公告)日：2024-03-19

申请号：US17315996

申请日：2021-05-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Dexin Kong ,  Takashi Ando ,  Kangguo Cheng ,  Juntao Li

IPC: H10N70/00 ,  H10N70/20

CPC classification number: H10N70/828 ,  H10N70/826 ,  H10N70/8418 ,  H10N70/883 ,  H10N70/8833 ,  H10N70/023 ,  H10N70/026 ,  H10N70/061 ,  H10N70/24

Abstract: A semiconductor device with resistive memory includes a bottom electrode disposed on a base structure, the bottom electrode having a structure that tapers up from the base structure to a tip of the bottom electrode. The semiconductor device also includes sidewall spacers on the sides of the bottom electrode, an interlayer dielectric deposition (ILD) outside the sidewall spacers, and a top dielectric layer disposed over the bottom electrode, and the sidewall spacers. The semiconductor device further includes a top electrode deposited over the bottom electrode within the sidewall spacers. A filament formation region is formed at the tip of the bottom electrode.

公开(公告)号：US11923363B2

公开(公告)日：2024-03-05

申请号：US17480063

申请日：2021-09-20

Applicant: International Business Machines Corporation

Inventor： Julien Frougier ,  Ruilong Xie ,  Kangguo Cheng ,  Chanro Park ,  Juntao Li

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L27/092 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78696

Abstract: Illustrative embodiments provide techniques for fabricating semiconductor structures having bottom isolation and enhanced carrier mobility for both nFET and pFET devices. For example, in one illustrative embodiment, a semiconductor structure includes a semiconductor substrate, a first dielectric layer disposed on the semiconductor substrate, a bottom source/drain region disposed on the first dielectric layer and isolated from the semiconductor substrate by the first dielectric layer, a second dielectric layer disposed on the bottom source/drain region and a top source/drain region disposed on the second dielectric layer and isolated from the bottom source/drain region by the second dielectric layer. The bottom source/drain region comprises a compressive pFET epitaxy and the top source/drain region comprises a tensile nFET epitaxy.