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    METAL HARD MASK FOR PRECISE TUNING OF MANDRELS
    5.
    发明公开
    METAL HARD MASK FOR PRECISE TUNING OF MANDRELS 审中-公开

    公开(公告)号：US20240038535A1

    公开(公告)日：2024-02-01

    申请号：US17875756

    申请日：2022-07-28

    申请人： International Business Machines Corporation

    发明人： Joe Lee ,  Yann Mignot ,  Christopher J. Penny ,  Koichi Motoyama

    IPC分类号： H01L21/033 ,  H01L21/027

    CPC分类号： H01L21/0337 ,  H01L21/0276 ,  H01L21/0335 ,  H01L21/0332

    摘要： A method of forming a mandrel for use in a pitch doubling process is provided in which a metal hard mask is inserted between a mandrel material layer and a soft mask. The insertion of the metal hard mask allows for easier pattern transfer into the mandrel material layer and avoids many issues encountered during multi-patterning steps. The insertion of the metal hard mask forms a square mandrel that has a flat top due to durability against etch and ability to wet strip the metal hard mask. The metal hard mask can be tuned before pattern transfer into the underlying mandrel material layer to provide a hard mask pattern that is smaller or larger than the pattern without performing such tuning. The method also can be used to protect the downstream non-mandrel processes where selectivity is crucial.

    Line formation with cut-first tip definition
    9.
    发明授权
    Line formation with cut-first tip definition 有权

    公开(公告)号：US11798842B2

    公开(公告)日：2023-10-24

    申请号：US17482939

    申请日：2021-09-23

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Chanro Park ,  Koichi Motoyama ,  Hsueh-Chung Chen ,  Yann Mignot

    IPC分类号： H01L21/768 ,  H01L21/306

    CPC分类号： H01L21/76843 ,  H01L21/30608 ,  H01L21/7688 ,  H01L21/76879 ,  H01L21/76897

    摘要： Semiconductor devices and methods of forming conductive lines in the same include forming a cut region in a first dielectric layer, the cut region having a first width. A second dielectric plug is formed in the cut region. A mask is formed, over the first dielectric layer, that defines at least one trench region that crosses the second dielectric plug, with the at least one trench region having a second width that is smaller than the first width. Material from the first dielectric layer in the trench regions is etched away, using a selective anisotropic etch that leaves the second dielectric plug in place, to form trenches in the first dielectric layer. Conductive material is deposited in the trenches to form conductive lines that are separated by the second dielectric plug.

    Interconnect structures including self aligned vias
    10.
    发明授权
    Interconnect structures including self aligned vias 有权

    公开(公告)号：US11735468B2

    公开(公告)日：2023-08-22

    申请号：US17541450

    申请日：2021-12-03

    申请人： International Business Machines Corporation

    发明人： Chih-Chao Yang ,  Terry A. Spooner ,  Koichi Motoyama ,  Shyng-Tsong Chen

    IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/528

    CPC分类号： H01L21/76802 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/5226

    摘要： Back end of line metallization structures and methods for fabricating self-aligned vias. The structures generally include a first interconnect structure disposed above a substrate. The first interconnect structure includes a metal line formed in a first interlayer dielectric. A second interconnect structure overlies the first interconnect structure. The second interconnect structure includes a second cap layer on the first interlayer dielectric, a second interlayer dielectric thereon, and at least one self-aligned via in the second interlayer dielectric conductively coupled to at least a portion of the metal line of the first interconnect structure, wherein any misalignment of the at least one self-aligned via results in the at least one self-aligned via landing on both the metal line of the first interconnect structure and the second cap layer. The second cap layer is an insulating material.