公开(公告)号：US20130019553A1

公开(公告)日：2013-01-24

申请号：US13638499

申请日：2011-03-31

申请人： Kohji Kohno ,  Motokuni Itakusu ,  Masaharu Sato ,  Takuo Uehara ,  Yoshitsugu Okanaka ,  Tomonobu Shiraishi ,  Kenji Goto ,  Sho Yamanaka

发明人： Kohji Kohno ,  Motokuni Itakusu ,  Masaharu Sato ,  Takuo Uehara ,  Yoshitsugu Okanaka ,  Tomonobu Shiraishi ,  Kenji Goto ,  Sho Yamanaka

IPC分类号： F27D1/00 ,  E04B1/78

CPC分类号： F27D1/0009 ,  F27D1/0013 ,  F27D1/0016 ,  F27D1/1621

摘要： Disclosed are a fibrous insulation block which can improve work efficiency of lining construction in various types of refractory furnace in iron works, and a construction method for a heated furnace-surface lining using the same. Specifically disclosed is a fibrous insulation block which comprises: a unit block (2) formed by laminating fibrous insulation blankets under pressure; a packing material (3) which has a pressing surface abutting section (5) covering at least a part of each pressing surface (2a, 2b) which are the side surfaces of the unit block in the direction in which the blankets are laminated, and a heating surface protection section (6) connected to the pressing surface abutting section so as to cover at least a part of a heating surface (2c) of the unit block, and in which a boundary section (7) between the pressing surface abutting section and the heating surface protection section covers an angle section formed by the pressing surfaces and the heating surface of the unit block; and a binding band (4) which maintains the shape of the unit block (2) using the packing material (3). The heating surface protection section (6) of the packing material (3) can be moved by the removal of the binding band and disposed on the same plane as the pressing surface abutting section, and has handhold sections (10) provided therein.

摘要翻译： 公开了一种纤维绝缘块，其可以提高铁工厂中各种耐火炉的衬砌施工的工作效率，以及使用其的加热的炉面衬砌的施工方法。 具体公开了一种纤维绝缘块，其包括：通过在压力下层压纤维绝缘层而形成的单元块（2） 一种包装材料（3），其具有覆盖所述单元块的层叠方向的侧面的各按压面（2a，2b）的至少一部分的按压面抵接部（5），以及 与所述按压面抵接部连接以覆盖所述单元块的加热面（2c）的至少一部分的加热面保护部（6），所述加压面抵接部 并且所述加热面保护部覆盖由所述单元块的所述按压面和所述加热面形成的角部; 以及使用包装材料（3）保持单元块（2）的形状的装订带（4）。 包装材料（3）的加热表面保护部分（6）可以通过移除装订带而移动，并且设置在与按压表面抵接部分相同的平面上，并且具有设置在其中的手持部分（10）。

公开(公告)号：US08116050B2

公开(公告)日：2012-02-14

申请号：US12539251

申请日：2009-08-11

申请人： Toshinobu Nagasawa ,  Tetsushi Toyooka ,  Masaharu Sato

发明人： Toshinobu Nagasawa ,  Tetsushi Toyooka ,  Masaharu Sato

IPC分类号： H02H9/00

CPC分类号： H01L27/0921 ,  H03K17/0822

摘要： To provide a semiconductor integrated circuit including: a detection circuit that detects an occurrence of latch up and can be configured while adopting a layout configuration that suppresses the occurrence of latch up; and a recovery unit that enables a recovery from the latch up without cutting off a positive potential. The semiconductor integrated circuit includes: a n-channel MOS transistor 7 that is formed on a P-type region 3 on a semiconductor substrate; and a latch up detection circuit that detects an occurrence of latch up in the n-channel MOS transistor 7. The latch up detection circuit includes: a n-MOS transistor structure 12 in which a source 10 and a back gate 8 are connected in common with a source 5 and the back gate 8 of the n-channel MOS transistor 7; and an electric current detection unit 15 that detects an electric current flowing to a drain 9 of the n-MOS transistor structure 12.

摘要翻译： 提供一种半导体集成电路，包括：检测电路，其检测闩锁的发生，并且可以在采用抑制闭锁发生的布局配置的同时进行配置; 以及恢复单元，其能够从闩锁恢复而不切断正电位。 半导体集成电路包括：形成在半导体基板上的P型区域3上的n沟道MOS晶体管7; 以及锁存检测电路，其检测n沟道MOS晶体管7中的锁存的发生。锁存检测电路包括：n-MOS晶体管结构12，其中源极10和背栅极8共同连接 源极5和n沟道MOS晶体管7的背栅极8; 以及电流检测单元15，其检测流向n-MOS晶体管结构12的漏极9的电流。

公开(公告)号：US07924090B2

公开(公告)日：2011-04-12

申请号：US12445836

申请日：2007-10-29

申请人： Noriyuki Fujita ,  Shigeo Masai ,  Masaharu Sato

发明人： Noriyuki Fujita ,  Shigeo Masai ,  Masaharu Sato

IPC分类号： H03F3/30

CPC分类号： H03F1/52 ,  H03F1/56 ,  H03F3/45475 ,  H03F2203/45136 ,  H03F2203/45576

摘要： An amplifying device for setting input impedance at several GΩ to several tens of GΩ and improving an ESD withstand current rating is provided.An ECM is connected to an input terminal 21 and frequency characteristics become flat to a voice band by high input impedance of a CMOS amplifier 20 and the input impedance is set at several GΩ to several tens of GΩ and thereby, response time after detecting a loud voice or turning on a power source of the ECM is speeded up and desired electrical characteristics are achieved. A path for releasing a surge voltage which occurs during assembly in the outside of an IC and intrudes from the input terminal 21 to a power source terminal or an earth terminal without an influence on a signal (20 Hz to 20 kHz) of a voice band entering from the input terminal 21 can be constructed by connecting a P-channel MOS transistor 27 and an N-channel MOS transistor 28 as an ESD protective element.

摘要翻译： 用于设置几个G＆OHgr的输入阻抗的放大装置; 到几十G＆OHgr; 并提供了ESD耐受额定电流。 ECM连接到输入端子21，并且频率特性通过CMOS放大器20的高输入阻抗而变得平坦到语音频带，并且输入阻抗被设置为几个G＆OHgr; 到几十G＆OHgr; 因此，检测到大声音或者打开ECM的电源之后的响应时间被加速并达到期望的电特性。 用于释放在IC外部组装期间发生的浪涌电压的路径，并且从输入端子21入射到电源端子或接地端子，而不影响声频带的信号（20Hz至20kHz） 可以通过连接作为ESD保护元件的P沟道MOS晶体管27和N沟道MOS晶体管28构成从输入端子21进入。

公开(公告)号：US07714389B2

公开(公告)日：2010-05-11

申请号：US12289267

申请日：2008-10-23

申请人： Masaharu Sato

发明人： Masaharu Sato

IPC分类号： H01L23/62

CPC分类号： H01L27/0744 ,  H01L27/0262

摘要： A semiconductor device includes a pair of transistors formed in a first conductive type semiconductor substrate. Each of the transistors contains a collector region of a second conductive type, opposite to the first conductive type, formed in the semiconductor substrate, a base region of the first conductive type formed in the collector region, and an emitter region of the second conductive type formed in the base region, the collector region of one transistor of the pair of transistors being separated from that of the other transistor. The semiconductor device further includes a first region of the first conductive type formed between the collector regions of the pair of transistors, and a buried layer of the second conductive type formed in the semiconductor substrate under the collector region of one transistor of the pair of transistors to connect the collector regions of the transistors therethrough.

摘要翻译： 半导体器件包括形成在第一导电类型半导体衬底中的一对晶体管。 每个晶体管包含形成在半导体衬底中的与第一导电类型相反的第二导电类型的集电极区域，形成在集电极区域中的第一导电类型的基极区域和第二导电类型的发射极区域 形成在基极区域中的一对晶体管中的一个晶体管的集电极区域与另一个晶体管的集电极区域分离。 半导体器件还包括形成在该对晶体管的集电极区域之间的第一导电类型的第一区域和形成在该半导体衬底中的一个晶体管的集电极区域下的半导体衬底中的第二导电类型的掩埋层 以通过其连接晶体管的集电极区域。

公开(公告)号：US20090108406A1

公开(公告)日：2009-04-30

申请号：US12289267

申请日：2008-10-23

申请人： Masaharu Sato

发明人： Masaharu Sato

IPC分类号： H01L27/082

CPC分类号： H01L27/0744 ,  H01L27/0262

摘要： A semiconductor device includes a pair of transistors formed in a first conductive type semiconductor substrate. Each of the transistors contains a collector region of a second conductive type, opposite to the first conductive type, formed in the semiconductor substrate, a base region of the first conductive type formed in the collector region, and an emitter region of the second conductive type formed in the base region, the collector region of one transistor of the pair of transistors being separated from that of the other transistor. The semiconductor device further includes a first region of the first conductive type formed between the collector regions of the pair of transistors, and a buried layer of the second conductive type formed in the semiconductor substrate under the collector region of one transistor of the pair of transistors to connect the collector regions of the transistors therethrough.

摘要翻译： 半导体器件包括形成在第一导电类型半导体衬底中的一对晶体管。 每个晶体管包含形成在半导体衬底中的与第一导电类型相反的第二导电类型的集电极区域，形成在集电极区域中的第一导电类型的基极区域和第二导电类型的发射极区域 形成在基极区域中的一对晶体管中的一个晶体管的集电极区域与另一个晶体管的集电极区域分离。 半导体器件还包括形成在该对晶体管的集电极区域之间的第一导电类型的第一区域和形成在该半导体衬底中的一个晶体管的集电极区域下的半导体衬底中的第二导电类型的掩埋层 以通过其连接晶体管的集电极区域。

公开(公告)号：US07432170B2

公开(公告)日：2008-10-07

申请号：US11017695

申请日：2004-12-22

申请人： Hiroaki Ohkubo ,  Ryota Yamamoto ,  Masayuki Furumiya ,  Masaharu Sato ,  Kuniko Kikuta ,  Makoto Nakayama ,  Yasutaka Nakashiba

发明人： Hiroaki Ohkubo ,  Ryota Yamamoto ,  Masayuki Furumiya ,  Masaharu Sato ,  Kuniko Kikuta ,  Makoto Nakayama ,  Yasutaka Nakashiba

IPC分类号： H01L21/20

CPC分类号： H01L28/40 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： On a silicon substrate, a first insulation layer, a lower conductive layer, a capacitor-insulator layer, and an upper conductive layer are formed in that order. Then, a first resist pattern is formed, the upper conductive layer is etched to form an upper electrode, and the capacitor-insulator layer is successively etched partway under the same etching condition as that of the upper conductive layer. Next, second resist pattern is formed, the remaining part of the capacitor-insulator layer is etched to form a second insulation layer, and the lower conductive layer is successively etched under the same etching condition as that of the capacitor-insulator layer so as to form a lower electrode and a lower wiring. In this manner, an MiM capacitor element constituted by the upper electrode, a part of the second insulation layer, and the lower electrode can be fabricated.

摘要翻译： 在硅衬底上依次形成第一绝缘层，下导电层，电容器 - 绝缘体层和上导电层。 然后，形成第一抗蚀剂图案，蚀刻上导电层以形成上电极，并且在与上导电层的蚀刻条件相同的蚀刻条件下，电容器 - 绝缘体层被连续蚀刻。 接下来，形成第二抗蚀剂图案，蚀刻电容器 - 绝缘体层的其余部分以形成第二绝缘层，并且在与电容器 - 绝缘体层的蚀刻条件相同的蚀刻条件下，依次蚀刻下导电层，以便 形成下电极和下布线。 以这种方式，可以制造由上电极，第二绝缘层的一部分和下电极构成的MiM电容器元件。

公开(公告)号：US07414086B2

公开(公告)日：2008-08-19

申请号：US11409041

申请日：2006-04-24

申请人： Tsuneo Kimura ,  Masaharu Sato

发明人： Tsuneo Kimura ,  Masaharu Sato

IPC分类号： C08K3/36

CPC分类号： C08L83/06 ,  C08L83/00

摘要： RTV organopolysiloxane compositions comprising (A) a diorganopolysiloxane having hydroxyl or alkoxysilyl groups at both ends, (B) a polyoxypropylene-modified silicone, (C) wet silica, and (D) a silane or siloxane having at least three silicon-bonded hydrolyzable groups have improved sag control and cure at room temperature into products with improved rubber physical properties and durability.

摘要翻译： RTV有机聚硅氧烷组合物，其包含（A）在两端具有羟基或烷氧基甲硅烷基的二有机聚硅氧烷，（B）聚氧丙烯改性硅氧烷，（C）湿二氧化硅和（D）具有至少三个硅键合的可水解基团的硅烷或硅氧烷 在室温下将下垂控制和固化改进成具有改进的橡胶物理性能和耐久性的产品。

公开(公告)号：US07270335B2

公开(公告)日：2007-09-18

申请号：US10768641

申请日：2004-02-02

申请人： Koji Hio ,  Takaaki Uno ,  Masaharu Sato

发明人： Koji Hio ,  Takaaki Uno ,  Masaharu Sato

IPC分类号： B60G17/015

CPC分类号： B60G17/0157 ,  F16F15/03

摘要： An electromagnetic suspension apparatus for an automotive vehicle, employs an electromagnetic actuator interleaved between a sprung mass and an unsprung mass and arranged in parallel with a suspension spring element, and an electric motor built in the electromagnetic actuator for driving the electromagnetic actuator. A motor controller calculates a displacement input, such as a suspension stroke acceleration and a suspension velocity, transmitted to the electromagnetic actuator, and controls the motor to bring a suspension damping force closer to a desired damping force suited for the displacement input. The motor controller calculates an internal inertia force of the electromagnetic actuator, and corrects or compensates for a motor output by the internal inertia force of the electromagnetic actuator.

摘要翻译： 一种用于机动车辆的电磁悬挂装置，采用在悬挂质量块和簧下质量块之间交错并与悬架弹簧元件平行布置的电磁致动器，以及内置于电磁致动器中的用于驱动电磁致动器的电动机。 电机控制器计算传递到电磁致动器的位移输入，例如悬架行程加速度和悬架速度，并且控制马达使悬架阻尼力更接近适于位移输入的期望阻尼力。 电机控制器计算电磁执行器的内部惯性力，并通过电磁执行器的内部惯性力校正或补偿电机输出。

公开(公告)号：US06339337B1

公开(公告)日：2002-01-15

申请号：US09048045

申请日：1998-03-26

申请人： Shuichi Matsuda ,  Keiichiro Kata ,  Ryoji Sato ,  Masaharu Sato

发明人： Shuichi Matsuda ,  Keiichiro Kata ,  Ryoji Sato ,  Masaharu Sato

IPC分类号： G01R3102

CPC分类号： G01R31/311

摘要： An infrared ray test for a semiconductor chip is conducted by irradiating infrared ray onto a bottom surface of a semiconductor chip, receiving the infrared ray reflected from a bonding pad and displaying the image of the bonding pad on a monitor. The image obtained from the infrared ray has information whether the bonding pad itself or a portion of the silicon substrate underlying the bonding pad has a defect or whether or not there is a deviation of the bonding pad with respect to the bump.

摘要翻译： 通过将红外线照射到半导体芯片的底面上，接收从接合焊盘反射的红外线并将接合焊盘的图像显示在监视器上，进行半导体芯片的红外线测试。 从红外线获得的图像具有关于焊盘本身或接合焊盘下方的硅衬底的一部分是否具有缺陷的焊盘的位置，或者接合焊盘相对于凸块是否存在偏差的信息。

公开(公告)号：US5304830A

公开(公告)日：1994-04-19

申请号：US22133

申请日：1993-02-25

申请人： Masaharu Sato

发明人： Masaharu Sato

IPC分类号： H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  H01L29/76 ,  H01L29/00 ,  H01L29/94

CPC分类号： H01L27/0623

摘要： A semiconductor integrated circuit device is fabricated from a complementary inverter circuit and an emitter coupled logic circuit, and an n-type well assigned to a p-channel type transistor extends beneath a p-type well assigned to an n-channel type transistor for partially overlapping therewith, thereby increasing capacitance across the p-n junction for eliminating noises from power voltages.

摘要翻译： 半导体集成电路器件由互补反相器电路和发射极耦合逻辑电路制成，分配给p沟道型晶体管的n型阱在分配给n沟道型晶体管的p型阱下方部分地部分地 与之重叠，从而增加pn结上的电容，以消除电源电压的噪声。