公开(公告)号：US08270840B2

公开(公告)日：2012-09-18

申请号：US12818361

申请日：2010-06-18

Applicant: Jiin Lai

Inventor： Jiin Lai

IPC: H04B10/02 ,  H04B10/04

CPC classification number: G06F13/426 ,  G06F13/385

Abstract: An optical USB device includes an electro-optical converter configured to receive optical signals from an optical fiber and to convert them into first electrical signals and configured to receive second electrical signals and to convert them into optical signals for transmission to the optical fiber. A USB 3.0 pin-compatible connector is coupled to the electro-optical converter. The pin-compatible connector is configured for coupling to a USB 3.0 connector of another USB device. The pin-compatible connector includes a first pair of pins configured for transmitting the first electrical signals from the optical USB device. The pin-compatible connector also includes a second pair of pins configured for receiving the second electrical signals into the optical USB device. The pin-compatible connector also includes a third pair of pins configured for transceiving third electrical signals according to a non-USB serial bus interface protocol to control and configure the electro-optical converter.

Abstract translation: 光学USB装置包括电光转换器，其被配置为从光纤接收光信号并将其转换为第一电信号并且被配置为接收第二电信号并将其转换成用于传输到光纤的光信号。 USB 3.0引脚兼容的连接器耦合到电光转换器。 引脚兼容连接器被配置为耦合到另一个USB设备的USB 3.0连接器。 引脚兼容连接器包括被配置为从光学USB设备传输第一电信号的第一对引脚。 引脚兼容连接器还包括被配置为将第二电信号接收到光学USB设备中的第二对引脚。 引脚兼容连接器还包括第三对引脚，其被配置用于根据非USB串行总线接口协议收发第三电信号，以控制和配置电光转换器。

公开(公告)号：US08234416B2

公开(公告)日：2012-07-31

申请号：US12818342

申请日：2010-06-18

Applicant: Jiin Lai

Inventor： Jiin Lai

IPC: G06F3/00 ,  G06F15/00

CPC classification number: G06F13/4081 ,  G06F2213/0042

Abstract: An apparatus configured to couple to a universal serial bus (USB) 3.0 connector. The apparatus includes a management controller configured to couple to the USB 3.0 connector. The management controller is configured to detect from behavior on the D+ and D− pins of the USB 3.0 connector whether a device plugged into the USB 3.0 connector is a conventional USB 3.0 device or an optical USB device, where the optical USB device employs one of the D+ and D− pins of the USB 3.0 connector to transmit a data signal and the other to transmit a clock signal.

Abstract translation: 一种被配置为耦合到通用串行总线（USB）3.0连接器的装置。 该装置包括配置成耦合到USB 3.0连接器的管理控制器。 管理控制器被配置为根据USB 3.0连接器的D +和D-引脚的行为来检测插入USB 3.0连接器的设备是否是传统的USB 3.0设备或光学USB设备，其中光学USB设备采用 USB 3.0连接器的D +和D-引脚传输数据信号，另一个发送时钟信号。

公开(公告)号：US20110255873A1

公开(公告)日：2011-10-20

申请号：US12950122

申请日：2010-11-19

Applicant: Jinkuan Tang ,  Jiin Lai

Inventor： Jinkuan Tang ,  Jiin Lai

IPC: H04B10/02

CPC classification number: H04B10/40

Abstract: An optical transceiver module includes a receiving unit, a transmission driving unit, and a terminal control unit. The receiving unit outputs a receiver lost signal. The transmission driving unit includes a positive receiving signal terminal and a negative receiving signal terminal. The terminal control unit is coupled between the positive receiving signal terminal and the negative receiving signal terminal. The terminal control unit controls whether a differential terminator impedance is coupled between the positive receiving signal terminal and the negative receiving signal terminal according to the receiver lost signal.

Abstract translation: 光收发模块包括接收单元，传输驱动单元和终端控制单元。 接收单元输出接收机丢失信号。 发送驱动单元包括正接收信号端子和负接收信号端子。 终端控制单元耦合在正接收信号端子和负接收信号端子之间。 终端控制单元根据接收机丢失信号来控制差分终端阻抗是否连接在正接收信号端子和负接收信号端子之间。

公开(公告)号：US20110243568A1

公开(公告)日：2011-10-06

申请号：US12818361

申请日：2010-06-18

Applicant: Jiin Lai

Inventor： Jiin Lai

IPC: H04B10/28

CPC classification number: G06F13/426 ,  G06F13/385

Abstract: An optical USB device includes an electro-optical converter configured to receive optical signals from an optical fiber and to convert them into first electrical signals and configured to receive second electrical signals and to convert them into optical signals for transmission to the optical fiber. A USB 3.0 pin-compatible connector is coupled to the electro-optical converter. The pin-compatible connector is configured for coupling to a USB 3.0 connector of another USB device. The pin-compatible connector includes a first pair of pins configured for transmitting the first electrical signals from the optical USB device. The pin-compatible connector also includes a second pair of pins configured for receiving the second electrical signals into the optical USB device. The pin-compatible connector also includes a third pair of pins configured for transceiving third electrical signals according to a non-USB serial bus interface protocol to control and configure the electro-optical converter.

Abstract translation: 光学USB装置包括电光转换器，其被配置为从光纤接收光信号并将其转换为第一电信号并且被配置为接收第二电信号并将其转换成用于传输到光纤的光信号。 USB 3.0引脚兼容的连接器耦合到电光转换器。 引脚兼容连接器被配置为耦合到另一个USB设备的USB 3.0连接器。 引脚兼容连接器包括被配置为从光学USB设备传输第一电信号的第一对引脚。 引脚兼容连接器还包括被配置为将第二电信号接收到光学USB设备中的第二对引脚。 引脚兼容连接器还包括第三对引脚，其被配置用于根据非USB串行总线接口协议收发第三电信号，以控制和配置电光转换器。

公开(公告)号：US07610497B2

公开(公告)日：2009-10-27

申请号：US11048191

申请日：2005-02-01

Applicant: Ruei-Ling Lin ,  Jiin Lai ,  Hung-Yi Kuo

Inventor： Ruei-Ling Lin ,  Jiin Lai ,  Hung-Yi Kuo

IPC: G06F1/26

CPC classification number: G06F1/3203 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/172

Abstract: A core logic coupled to a main memory of a computer, comprising an analyzer and a power management unit. The analyzer monitors access request traffic load of main memory. The power management unit employs various power performance trade-off activities with the knowledge of the monitored traffic load according to the state machine.

Abstract translation: 耦合到计算机的主存储器的核心逻辑，包括分析器和电源管理单元。 分析仪监控主存储器的访问请求流量负载。 电力管理单元根据状态机采用各种电力性能权衡活动，了解监控的业务负载。

公开(公告)号：US07594058B2

公开(公告)日：2009-09-22

申请号：US11267498

申请日：2005-11-07

Applicant: Peter Chia ,  Chad Tsai ,  Jiin Lai ,  Edward Su ,  Chih-Kuo Kao

Inventor： Peter Chia ,  Chad Tsai ,  Jiin Lai ,  Edward Su ,  Chih-Kuo Kao

IPC: G06F13/36

CPC classification number: G06F13/36

Abstract: The present computing system using PCI-E architecture includes at least one first PCI-E port, a first port-arbiter, a first URD logic, a microprocessor, a DARD logic and a device arbiter. The first port-arbiter receives a data from the first PCI-E port. The first URD logic is coupled to said first port-arbiter. The first URD logic includes an onboard range table and a PCI-E device range table for detecting the data of onboard access or peer-to-peer access. The microprocessor receives and processes the data from the first URD logic for said onboard access. The DARD logic receives the data from the microprocessor. The DARD logic decodes a device range of a downstream request of the data. The device arbiter is coupled to the DARD logic and the first URD logic for dispatching the data to one of the first PCI-E port.

Abstract translation: 使用PCI-E架构的本计算系统包括至少一个第一PCI-E端口，第一端口仲裁​​器，第一URD逻辑，微处理器，DARD逻辑和设备仲裁器。 第一个端口仲裁器从第一个PCI-E端口接收数据。 第一URD逻辑耦合到所述第一端口仲裁​​器。 第一个URD逻辑包括板载范围表和PCI-E设备范围表，用于检测板上访问或对等访问的数据。 微处理器接收并处理来自用于所述板载存取的第一URD逻辑的数据。 DARD逻辑从微处理器接收数据。 DARD逻辑解码数据的下游请求的设备范围。 设备仲裁器耦合到DARD逻辑和第一个URD逻辑，用于将数据分配到第一个PCI-E端口之一。

公开(公告)号：US20080313471A1

公开(公告)日：2008-12-18

申请号：US12107206

申请日：2008-04-22

Applicant: Zhun Huang ,  Jiin Lai

Inventor： Zhun Huang ,  Jiin Lai

IPC: H04K1/00

CPC classification number: G06F21/10 ,  G06F21/445 ,  G06F2221/2129

Abstract: An electronic system is provided, in which a smart chip, a smart chip controller, a processor, a system memory, and an access management module is provided. The smart chip controller communicates with the smart chip. The processor performs a mutual authentication with the smart chip. The system memory is accessible to the smart chip and the processor. The access management module is coupled between the processor and the smart chip controller. The access management module prevents the processor accessing a certain range of the system memory according to a block command from the smart chip controller, in response of that the mutual authentication between the processor and the smart chip is failed.

Abstract translation: 提供了一种电子系统，其中提供智能芯片，智能芯片控制器，处理器，系统存储器和访问管理模块。 智能芯片控制器与智能芯片通信。 处理器与智能芯片执行相互认证。 智能芯片和处理器可以访问系统内存。 访问管理模块耦合在处理器和智能芯片控制器之间。 响应于处理器和智能芯片之间的相互认证失败，访问管理模块防止处理器根据来自智能芯片控制器的块命令访问系统存储器的特定范围。

公开(公告)号：US20080046618A1

公开(公告)日：2008-02-21

申请号：US11876579

申请日：2007-10-22

Applicant: Ruei-Ling Lin ,  Jiin Lai

Inventor： Ruei-Ling Lin ,  Jiin Lai

IPC: G06F13/36

CPC classification number: G06F13/4217

Abstract: A data transmission coordinating method is used between a central processing unit and a bridge chip of a computer system. By entering the computer system into a coordinating state, the data transmission coordinating method is executed. The bridge chip and the CPU are informed of maximum bit numbers of each other for data transmission therebetween via the front side bus. Then, a commonly operable maximum bit number for data transmission between the CPU and the bridge chip can be coordinated according to the first and second maximum bit numbers. Once the commonly operable maximum bit number is determined, the CPU is reset to operate with the commonly operable maximum bit number. The maximum bit numbers are those of bus transmission width or bus transmission speed.

Abstract translation: 在计算机系统的中央处理单元和桥接芯片之间使用数据传输协调方法。 通过将计算机系统进入协调状态，执行数据传输协调方法。 通过桥芯片和CPU通过相互之间的最大位数，以经由前端总线进行数据传输。 然后，可以根据第一和第二最大比特数来协调CPU和桥接芯片之间用于数据传输的通用可操作的最大比特数。 一旦确定了通用可操作的最大位数，则CPU被复位以通常可操作的最大位数进行操作。 最大位数是总线传输宽度或总线传输速度。

公开(公告)号：US07082501B2

公开(公告)日：2006-07-25

申请号：US10405571

申请日：2003-04-02

Applicant: Wei-Long Chen ,  Jiin Lai ,  Wayne Tseng

Inventor： Wei-Long Chen ,  Jiin Lai ,  Wayne Tseng

IPC: G06F12/00

CPC classification number: G06F13/1663 ,  G06F12/0817

Abstract: A DSM system includes a local node, a first remote node, and a second remote nodes. The data access method for a remote node to access a local node in the DSM system includes the steps of directly receiving data of a local memory line from a local memory of the local node, and transmitting the data to the first remote node when the local memory line is in HOME-N or SHARED status; directly receiving data of the local memory line from the second remote node, and transmitting the data to the first remote node when the local memory line is in a GONE status; and asserting a transaction to a system bus to read data of the local memory line, receiving the data via the system bus, and transmitting the data to the first remote node when the local memory line is in HOME-M status.

公开(公告)号：US07051148B2

公开(公告)日：2006-05-23

申请号：US10055558

申请日：2002-01-22

Applicant: Jiin Lai ,  Chau-Chad Tsai ,  Chi-Che Tsai ,  Wen-Hao Chuang ,  Chun-Yuan Su

Inventor： Jiin Lai ,  Chau-Chad Tsai ,  Chi-Che Tsai ,  Wen-Hao Chuang ,  Chun-Yuan Su

IPC: G06F13/36 ,  G06F13/42

CPC classification number: G06F13/4059

Abstract: A data transmission sequencing method is disclosed. A data read operation from a primary bus to a secondary bus can be executed without having to wait for the complete transfer of write data stored in posted write buffer transferring to the primary bus, as long as the secondary bus is not in use. In the mean time of the primary bus issues a read operation to the secondary bus, the secondary bus can issues write operation to the bridging device when the secondary bus is not in use. Similarly, there is no need to wait for the completion of read operation. With this type of data transmission sequencing mechanism, idle sessions in a conventional transmission sequencing method are eliminated leading to a higher data transmission rate.