公开(公告)号：US20050124134A1

公开(公告)日：2005-06-09

申请号：US10728983

申请日：2003-12-08

申请人： Chung-Peng Hao ,  Yi-Nan Chen

发明人： Chung-Peng Hao ,  Yi-Nan Chen

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76229 ,  H01L21/76224

摘要： Disclosed is a shallow trench isolation (STI) forming method for improving STI step uniformity. The method deposits an oxidation layer to a semiconductor structure formed with STIs. After a planarization material layer is formed on the oxidation, then CMP process is performed. By using the method of the present invention, the STI step uniformity can be raised.

摘要翻译： 公开了一种用于提高STI步长均匀性的浅沟槽隔离（STI）形成方法。 该方法将氧化层沉积到由STI形成的半导体结构。 在氧化后形成平坦化材料层后，进行CMP工艺。 通过使用本发明的方法，可以提高STI步进均匀性。

公开(公告)号：US20050032359A1

公开(公告)日：2005-02-10

申请号：US10715658

申请日：2003-11-18

申请人： Chung-Peng Hao ,  Yi-Nan Chen

发明人： Chung-Peng Hao ,  Yi-Nan Chen

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/4763 ,  H01L29/78

CPC分类号： H01L29/66553 ,  H01L21/28052 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/6659 ,  H01L29/7833

摘要： The invention provides a damascene gate process. A semiconductor substrate having a pad layer and an etch stop layer formed thereon is provided, and an insulating layer is formed to cover the etch stop layer, followed by forming an opening by partially removing the insulating layer, the etch stop layer, and the pad layer. A protective spacer is formed on the sidewall of the opening, wherein the top of the protective spacer is lower than the insulating layer. A gate conducting layer is then formed in the opening. The protective spacer and the insulating layer are removed to expose a portion of the semiconductor substrate and the etch stop layer. Implantation is then performed to form lightly doped drains. Agate spacer is then formed to cover the gate conducting layer. The etch stop layer and the pad layer are removed, and implantation is then performed to a form source/drain.

摘要翻译： 本发明提供一种镶嵌门工艺。 提供具有形成在其上的焊盘层和蚀刻停止层的半导体衬底，并且形成绝缘层以覆盖蚀刻停止层，随后通过部分去除绝缘层，蚀刻停止层和焊盘形成开口 层。 保护间隔件形成在开口的侧壁上，其中保护间隔物的顶部低于绝缘层。 然后在开口中形成栅极导电层。 去除保护间隔物和绝缘层以暴露半导体衬底和蚀刻停止层的一部分。 然后进行植入以形成轻掺杂的排水沟。 然后形成玛瑙垫片以覆盖栅极导电层。 去除蚀刻停止层和焊盘层，然后对形式源/漏极进行注入。

公开(公告)号：US07071075B2

公开(公告)日：2006-07-04

申请号：US10728983

申请日：2003-12-08

申请人： Chung-Peng Hao ,  Yi-Nan Chen

发明人： Chung-Peng Hao ,  Yi-Nan Chen

IPC分类号： H01L21/76

CPC分类号： H01L21/76229 ,  H01L21/76224

摘要： Disclosed is a shallow trench isolation (STI) forming method for improving STI step uniformity. The method deposits an oxidation layer to a semiconductor structure formed with STIs. After a planarization material layer is formed on the oxidation, then CMP process is performed. By using the method of the present invention, the STI step uniformity can be raised.

摘要翻译： 公开了一种用于提高STI步长均匀性的浅沟槽隔离（STI）形成方法。 该方法将氧化层沉积到由STI形成的半导体结构上。 在氧化后形成平坦化材料层后，进行CMP工艺。 通过使用本发明的方法，可以提高STI步长均匀性。

公开(公告)号：US06984566B2

公开(公告)日：2006-01-10

申请号：US10715658

申请日：2003-11-18

申请人： Chung-Peng Hao ,  Yi-Nan Chen

发明人： Chung-Peng Hao ,  Yi-Nan Chen

IPC分类号： H01L21/336

CPC分类号： H01L29/66553 ,  H01L21/28052 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/6659 ,  H01L29/7833

摘要： The invention provides a damascene gate process. A semiconductor substrate having a pad layer and an etch stop layer formed thereon is provided, and an insulating layer is formed to cover the etch stop layer, followed by forming an opening by partially removing the insulating layer, the etch stop layer, and the pad layer. A protective spacer is formed on the sidewall of the opening, wherein the top of the protective spacer is lower than the insulating layer. A gate conducting layer is then formed in the opening. The protective spacer and the insulating layer are removed to expose a portion of the semiconductor substrate and the etch stop layer. Implantation is then performed to form lightly doped drains. A gate spacer is then formed to cover the gate conducting layer. The etch stop layer and the pad layer are removed, and implantation is then performed to a form source/drain.

摘要翻译： 本发明提供一种镶嵌门工艺。 提供具有形成在其上的焊盘层和蚀刻停止层的半导体衬底，并且形成绝缘层以覆盖蚀刻停止层，随后通过部分去除绝缘层，蚀刻停止层和焊盘形成开口 层。 保护间隔件形成在开口的侧壁上，其中保护间隔物的顶部低于绝缘层。 然后在开口中形成栅极导电层。 去除保护间隔物和绝缘层以暴露半导体衬底和蚀刻停止层的一部分。 然后进行植入以形成轻掺杂的排水沟。 然后形成栅极间隔物以覆盖栅极导电层。 去除蚀刻停止层和焊盘层，然后对形式源/漏极进行注入。

公开(公告)号：US20050042819A1

公开(公告)日：2005-02-24

申请号：US10726434

申请日：2003-12-03

申请人： Chung-Peng Hao ,  Yi-Nan Chen ,  Ming-Cheng Chang

发明人： Chung-Peng Hao ,  Yi-Nan Chen ,  Ming-Cheng Chang

IPC分类号： H01L21/8234 ,  H01L21/8242 ,  H01L21/8244 ,  H01L27/108

CPC分类号： H01L27/10876 ,  H01L27/10838 ,  H01L27/10841

摘要： A double corner rounding process for a partial vertical cell. A first corner rounding process is performed after etching the substrate to form a shallow trench for device isolation. A second corner rounding process is performed after forming shallow trench isolations (STIs) and exposing the corner of the substrate at the active areas in the memory cell array region.

摘要翻译： 用于部分垂直单元的双角舍入处理。 在蚀刻基板之后进行第一个圆角化处理以形成用于器件隔离的浅沟槽。 在形成浅沟槽隔离（STI）并且在存储单元阵列区域中的有源区域处暴露基板的角部之后，进行第二个角圆化处理。

公开(公告)号：US08642479B2

公开(公告)日：2014-02-04

申请号：US13183358

申请日：2011-07-14

申请人： Chih-Ching Lin ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Chih-Ching Lin ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L21/302

CPC分类号： H01L21/76802 ,  H01L21/31144 ,  H01L21/32137

摘要： A method for forming an opening in a semiconductor device is provided, including: providing a semiconductor substrate with a silicon oxide layer, a polysilicon layer and a silicon nitride layer sequentially formed thereover; patterning the silicon nitride layer, forming a first opening in the silicon nitride layer, wherein the first opening exposes a top surface of the polysilicon layer; performing a first etching process, using gasous etchants including hydrogen bromide (HBr), oxygen (O2), and fluorocarbons (CxFy), forming a second opening in the polysilicon layer, wherein a sidewall of the polysilicon layer adjacent to the second opening is substantially perpendicular to a top surface of the silicon oxide layer, wherein x is between 1-5 and y is between 2-8; removing the silicon nitride layer; and performing a second etching process, forming a third opening in the silicon oxide layer exposed by the second opening.

摘要翻译： 提供了一种在半导体器件中形成开口的方法，包括：向半导体衬底提供其上顺序形成的氧化硅层，多晶硅层和氮化硅层; 图案化氮化硅层，在氮化硅层中形成第一开口，其中第一开口暴露多晶硅层的顶表面; 使用包括溴化氢（HBr），氧（O 2）和碳氟化合物（C x F y）的气体蚀刻剂进行第一蚀刻工艺，在多晶硅层中形成第二开口，其中与第二开口相邻的多晶硅层的侧壁基本上 垂直于氧化硅层的顶表面，其中x在1-5之间，y在2-8之间; 去除氮化硅层; 以及进行第二蚀刻工艺，在由所述第二开口暴露的所述氧化硅层中形成第三开口。

公开(公告)号：US08551881B2

公开(公告)日：2013-10-08

申请号：US13093735

申请日：2011-04-25

申请人： Shing-Yih Shih ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Shing-Yih Shih ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L21/44

CPC分类号： H01L21/304 ,  H01L21/76898

摘要： A method of bevel trimming a three dimensional (3D) semiconductor device is disclosed, comprising providing a substrate with stack layers thereon and through substrate vias (TSV) therein, wherein an edge of the substrate is curved, performing a bevel trimming step to the curved edge of the substrate for obtaining a planar edge, and thinning the substrate to expose the through substrate vias.

摘要翻译： 公开了一种斜面修整三维（3D）半导体器件的方法，包括提供衬底上的堆叠层，并通过其中的衬底通孔（TSV），其中衬底的边缘是弯曲的，对弯曲的 边缘，用于获得平面边缘，并且使基板变薄以暴露通过的基板通孔。

公开(公告)号：US08487397B2

公开(公告)日：2013-07-16

申请号：US13093742

申请日：2011-04-25

申请人： Jar-Ming Ho ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Jar-Ming Ho ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L23/52

CPC分类号： H01L23/485 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823475 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit with a self-aligned contact includes a substrate with a transistor formed thereover, a dielectric spacer, a protection barrier, and a conductive layer. The transistor includes a mask layer and a pair of insulating spacers formed on opposite sides of the mask layer. The dielectric spacer partially covers at least one of the insulating spacers of the transistor. The protection barrier is formed over the dielectric spacer. The conductive layer is formed over the mask layer, the protection barrier, the dielectric spacer, the insulating spacer and the dielectric spacer as a self-aligned contact for contacting a source/drain region of the transistor.

摘要翻译： 具有自对准接触的集成电路包括其上形成有晶体管的衬底，介电间隔物，保护屏障和导电层。 晶体管包括掩模层和形成在掩模层的相对侧上的一对绝缘间隔物。 电介质间隔物部分地覆盖晶体管的至少一个绝缘间隔物。 保护屏障形成在电介质间隔物上。 导电层形成在掩模层，保护屏障，电介质间隔物，绝缘间隔物和介电间隔物上，作为用于接触晶体管的源/漏区的自对准接触。

公开(公告)号：US20130099309A1

公开(公告)日：2013-04-25

申请号：US13281293

申请日：2011-10-25

申请人： Jeng-Hsing Jang ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Jeng-Hsing Jang ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66666 ,  H01L21/823487 ,  H01L27/0266 ,  H01L29/0692 ,  H01L29/4238 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A vertical MOSFET electrostatic discharge device is disclosed, including a substrate comprising a plurality of trenches, a recessed gate disposed in each trench, a drain region disposed between each of the two neighboring recessed gates, an electrostatic discharge implant region disposed under each drain region, and a source region surrounding and disposed under the recessed gates and the electrostatic discharge implant regions.

摘要翻译： 公开了一种垂直MOSFET静电放电装置，包括：包括多个沟槽的衬底;设置在每个沟槽中的凹入栅极，设置在两个相邻凹入栅极中的每一个之间的漏极区域，设置在每个漏极区域下方的静电放电注入区域， 以及围绕并设置在凹入栅极和静电放电注入区域下面的源极区域。

公开(公告)号：US08415729B2

公开(公告)日：2013-04-09

申请号：US13081500

申请日：2011-04-07

申请人： Tieh-Chiang Wu ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Tieh-Chiang Wu ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L27/108

CPC分类号： H01L29/7397 ,  H01L29/4236 ,  H01L29/66348

摘要： A power device with trenched gate structure, includes: a substrate having a first face and a second face opposing to the first face, a body region of a first conductivity type disposed in the substrate, a base region of a second conductivity type disposed in the body region, a cathode region of the first conductivity type disposed in the base region, an anode region of the second conductivity type disposed in the substrate at the second face a trench disposed in the substrate and extending from the first face into the body region, and the cathode region encompassing the trench, wherein the trench has a wavelike sidewall, a gate structure disposed in the trench and an accumulation region disposed in the body region and along the wavelike sidewall. The wavelike sidewall can increase the base current of the bipolar transistor and increase the performance of the IGBT.

摘要翻译： 具有沟槽栅极结构的功率器件包括：具有第一面和与第一面相对的第二面的衬底，设置在衬底中的第一导电类型的主体区域，设置在第二导电类型的基极区域 设置在所述基底区域中的所述第一导电类型的阴极区域，所述第二导电类型的阳极区域设置在所述基板的所述第二面处，所述沟槽设置在所述基板中并且从所述第一面延伸到所述主体区域中， 以及包围所述沟槽的阴极区域，其中所述沟槽具有波状侧壁，设置在所述沟槽中的栅极结构以及设置在所述体区中并沿着所述波浪形侧壁的堆积区域。 波浪形侧壁可以增加双极晶体管的基极电流并增加IGBT的性能。