公开(公告)号：US20120311510A1

公开(公告)日：2012-12-06

申请号：US13590300

申请日：2012-08-21

申请人： Fook-Luen Heng ,  Alexey Y. Lvov ,  Amith Singhee

发明人： Fook-Luen Heng ,  Alexey Y. Lvov ,  Amith Singhee

IPC分类号： G06F17/50

CPC分类号： G06F17/50

摘要： A method for estimating yield of a wafer having a plurality of chips printed thereon is provided which includes the following steps. The chip design is divided into a plurality of rectangular cells. A process window is determined for each of the cells. The focus and dose values on the wafer are measured and used to determine a Gaussian random component of the focus and dose values. The focus and dose values on the wafer are represented as a sum of a systematic component of the focus and dose values and the Gaussian random component. Wafer yield is estimated based on a number of the chips for which at each point (x, y) the focus and dose values, as represented as the sum of the systematic component of the focus and dose values and the Gaussian random component, belong to a corresponding one of the process windows.

摘要翻译： 提供了一种用于估计其上印有多个芯片的晶片的产量的方法，其包括以下步骤。 芯片设计分为多个矩形单元。 为每个单元确定一个处理窗口。 测量晶片上的焦点和剂量值，并用于确定焦点和剂量值的高斯随机分量。 晶片上的焦点和剂量值被表示为焦点和剂量值的系统分量与高斯随机分量之和。 基于芯片的数量估计晶片产量，其中每个点（x，y）的焦点和剂量值被表示为焦点和剂量值的系统分量与高斯随机分量的总和属于 相应的一个进程窗口。

公开(公告)号：US07962865B2

公开(公告)日：2011-06-14

申请号：US12175097

申请日：2008-07-17

申请人： Fook-Luen Heng ,  Mark Alan Lavin ,  Jin-Fuw Lee ,  Chieh-yu Lin ,  Jawahar Pundalik Nayak ,  Rama Nand Singh

发明人： Fook-Luen Heng ,  Mark Alan Lavin ,  Jin-Fuw Lee ,  Chieh-yu Lin ,  Jawahar Pundalik Nayak ,  Rama Nand Singh

IPC分类号： G06F17/20 ,  G06F19/00 ,  G03F1/00 ,  G21K5/00

CPC分类号： G06F17/5068

摘要： A system and method of employing patterning process statistics to evaluate layouts for intersect area analysis includes applying Optical Proximity Correction (OPC) to the layout, simulating images formed by the mask and applying patterning process variation distributions to influence and determine corrective actions taken to improve and optimize the rules for compliance by the layout. The process variation distributions are mapped to an intersect area distribution by creating a histogram based upon a plurality of processes for an intersect area. The intersect area is analyzed using the histogram to provide ground rule waivers and optimization.

摘要翻译： 使用图案化处理统计来评估交叉区域分析的布局的系统和方法包括对布局应用光学近似校正（OPC），模拟由掩模形成的图像并应用图案化过程变化分布来影响和确定纠正措施以改进和 优化布局符合规则。 通过基于交叉区域的多个处理创建直方图，将过程变化分布映射到交叉区域分布。 使用直方图分析交叉区域，以提供基本规则豁免和优化。

公开(公告)号：US07676775B2

公开(公告)日：2010-03-09

申请号：US11754947

申请日：2007-05-29

申请人： Howard Chen ,  Katherine V. Hawkins ,  Fook-Luen Heng ,  Louis Hsu ,  Xu Ouyang

发明人： Howard Chen ,  Katherine V. Hawkins ,  Fook-Luen Heng ,  Louis Hsu ,  Xu Ouyang

IPC分类号： G06F17/50

CPC分类号： G01R31/2894 ,  G01R31/31718 ,  G01R31/318314 ,  G11C29/10 ,  G11C29/56 ,  G11C29/56008

摘要： A method for determining the root causes of fail patterns in integrated circuit chips is provide wherein a known integrated circuit chip layout is used to identify a plurality of potential defects and a plurality of potential fail patterns in the integrated circuit chip. Correlations between the potential defects and the potential fail patterns that result from those defects are identified. Based on this identification, the potential fail patterns are grouped by common potential defect. An actual integrated circuit chip that is manufactured in accordance with the test layout is tested for failure patterns. These failure patterns are then compared to the groupings of potential fail patterns. When a match is found, that is when a given group of fail patterns is found in the actual integrated circuit chip, then the potential defect associated with the potential fail patterns to which the actual fail patterns are matched is identified. This defect is the root cause of the failure pattern in the actual chip.

摘要翻译： 提供了一种用于确定集成电路芯片中的故障模式的根本原因的方法，其中使用已知的集成电路芯片布局来识别集成电路芯片中的多个潜在缺陷和多个潜在故障模式。 鉴定出潜在缺陷与由这些缺陷产生的潜在失效模式之间的相关性。 基于此识别，潜在的故障模式由共同的潜在缺陷分组。 测试根据测试布局制造的实际集成电路芯片的故障模式。 然后将这些故障模式与潜在故障模式的分组进行比较。 当发现匹配时，即在实际的集成电路芯片中发现给定的一组故障模式时，识别与实际故障模式匹配的潜在故障模式相关联的潜在缺陷。 这个缺陷是实际芯片中故障模式的根本原因。

公开(公告)号：US20090089726A1

公开(公告)日：2009-04-02

申请号：US11865252

申请日：2007-10-01

申请人： Fook-Luen Heng ,  Mark A. Lavin ,  Jin-Fuw Lee ,  Thomas Ludwig ,  Rama Nand Singh ,  Fanchieh Yee

发明人： Fook-Luen Heng ,  Mark A. Lavin ,  Jin-Fuw Lee ,  Thomas Ludwig ,  Rama Nand Singh ,  Fanchieh Yee

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： A method for layout design includes steps or acts of: receiving a layout for design of an integrated circuit chip; designing mask shapes for the layout; transmitting the mask shapes to a litho simulator for generating wafer shapes; receiving the wafer shapes; calculating electrically equivalent gate lengths for the wafer shapes; analyzing the gate lengths to check for conformity against a threshold value, wherein the threshold value represents a desired value of electrically equivalent gate lengths; placing markers on the layout at those locations where the gate length violates the threshold value; and generating a histogram of gate lengths for comparing layouts for electrically equivalent gate lengths for layout quality.

摘要翻译： 一种用于布局设计的方法包括以下步骤或动作：接收用于集成电路芯片设计的布局; 设计布局的面具形状; 将掩模形状传送到用于产生晶片形状的光刻模拟器; 接收晶片形状; 计算晶片形状的等效栅极长度; 分析所述栅极长度以检查与阈值的一致性，其中所述阈值表示电等效栅极长度的期望值; 在栅极长度违反阈值的位置放置标记在布局上; 以及生成用于比较用于布局质量的电等效栅极长度的布局的栅极长度的直方图。

公开(公告)号：US07302671B2

公开(公告)日：2007-11-27

申请号：US11097552

申请日：2005-04-01

申请人： Fook-Luen Heng ,  Jin-Fuw Lee ,  Daniel L. Ostapko

发明人： Fook-Luen Heng ,  Jin-Fuw Lee ,  Daniel L. Ostapko

IPC分类号： G06F17/50

CPC分类号： H01L27/0207 ,  H01L27/092

摘要： An integrated circuit (IC) including at least one combinational logic path. The features in the combinational logic path are self compensating for out-of-focus effects. In particular, field effect transistor (FET) gates may be iso-focally spaced such that the gate (critical dimension) may move with changing focus, but the gate length remains the same. Alternately, logic circuits in a path may self-compensate for focus effects on individual circuits.

摘要翻译： 一种包括至少一个组合逻辑路径的集成电路（IC）。 组合逻辑路径中的特征是对于失焦效应的自我补偿。 特别地，场效应晶体管（FET）栅极可以是等焦点间隔开的，使得栅极（临界尺寸）可以随着焦点变化而移动，但是栅极长度保持相同。 或者，路径中的逻辑电路可以自我补偿各个电路上的聚焦效应。

公开(公告)号：US06986109B2

公开(公告)日：2006-01-10

申请号：US10438625

申请日：2003-05-15

申请人： Robert J. Allen ,  Fook-Luen Heng ,  Alexey Y. Lvov ,  Kevin W. McCullen ,  Sriram Peri ,  Gustavo E. Tellez

发明人： Robert J. Allen ,  Fook-Luen Heng ,  Alexey Y. Lvov ,  Kevin W. McCullen ,  Sriram Peri ,  Gustavo E. Tellez

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： The invention provides a method of modifying a hierarchical integrated circuit layout wherein the locations of hierarchical layout elements are represented with variables and formulae using these variables, which produces a formula-based hierarchical layout. These variables are constrained to be integers. The invention provides for a method for guiding the modification of the layout through an objective function defined on the same variables as the formula-based hierarchical layout. The invention simplifies the formula-based hierarchical layout by substituting constants for some of the variables, such that each of the formulae are reduced to expressions involving no more than two remaining variables. This produces a simplified layout equation and a simplified objective function. This also produces a partial solution to the hierarchical layout modification made up of the values selected for the constants.

摘要翻译： 本发明提供了一种修改分层集成电路布局的方法，其中使用这些变量的变量和公式表示分层布局元素的位置，这产生基于公式的分层布局。 这些变量被约束为整数。 本发明提供了一种用于通过与基于公式的分层布局相同的变量定义的目标函数来引导布局的修改的方法。 本发明通过将常数替换为一些变量来简化基于公式的分层布局，使得每个公式被减少到涉及不超过两个剩余变量的表达式。 这产生了简化的布局方程和简化的目标函数。 这也产生了对由常量选择的值组成的分层布局修改的部分解决方案。

公开(公告)号：US08108803B2

公开(公告)日：2012-01-31

申请号：US12603594

申请日：2009-10-22

申请人： Fook-Luen Heng ,  Xu Ouyang ,  Yunsheng Song ,  Yun-Yu Wang

发明人： Fook-Luen Heng ,  Xu Ouyang ,  Yunsheng Song ,  Yun-Yu Wang

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F2217/16

摘要： A method of failure detection of an integrated circuit (IC) layout includes determining a critical path distance between a first geometric feature of the IC layout and a second geometric feature of the IC layout; and comparing the determined critical path distance to a defined minimum critical path distance between the first and second geometric features, wherein the defined minimum critical path distance corresponds to a desired electrical property of the IC layout, independent of any geometric-based ground rule minimum distance for the IC layout; identifying any determined critical path distances that are less than the defined minimum critical path distance as a design violation; and modifying the IC layout by eliminating the identified design violations.

摘要翻译： 集成电路（IC）布局的故障检测方法包括确定IC布局的第一几何特征与IC布局的第二几何特征之间的关键路径距离; 以及将所确定的关键路径距离与所述第一和第二几何特征之间的限定的最小关键路径距离进行比较，其中所述限定的最小关键路径距离对应于所述IC布局的所需电气特性，独立于任何基于几何的基准规则最小距离 用于IC布局; 识别小于定义的最小关键路径距离的任何确定的关键路径距离作为设计违规; 并通过消除所识别的设计违规来修改IC布局。

公开(公告)号：US20110219344A1

公开(公告)日：2011-09-08

申请号：US12718567

申请日：2010-03-05

申请人： Fook-Luen Heng ,  Alexey Y. Lvov ,  Amith Singhee

发明人： Fook-Luen Heng ,  Alexey Y. Lvov ,  Amith Singhee

IPC分类号： G06F17/50

CPC分类号： G06F17/50

摘要： Techniques for estimating yield of an integrated circuit design, such as a very-large-scale integration (VLSI) design, are provided. In one aspect, a method for determining a probability of failure of a VLSI query design includes the following steps. A Voronoi diagram is built comprising a set of shapes that represent the design. The Voronoi diagram is converted into a rectangular grid comprising 2t×2s rectangular cells, wherein t and s are chosen so that one rectangular cell contains from about one to about five Voronoi cells. A probability of failure is computed for each of the cells in the grid. The cells in the grid are merged pairwise. A probability of failure for the merged cells is recomputed which accounts for a spatial correlation between the cells. The pairwise merge and recompute steps are performed s+t times to determine the probability of failure of the design.

摘要翻译： 提供了用于估计诸如大规模集成（VLSI）设计的集成电路设计的产量的技术。 一方面，用于确定VLSI查询设计的故障概率的方法包括以下步骤。 构建了一个Voronoi图，它包含一组代表设计的形状。 Voronoi图被转换为包括2t×2s矩形单元格的矩形网格，其中选择t和s，使得一个矩形单元格包含约一个至约五个Voronoi单元。 为网格中的每个单元格计算故障概率。 网格中的单元格成对合并。 重新计算合并的单元的故障概率，这说明了单元之间的空间相关性。 成对合并和重新计算步骤执行s + t次以确定设计失败的概率。

公开(公告)号：US20110099529A1

公开(公告)日：2011-04-28

申请号：US12603594

申请日：2009-10-22

申请人： Fook-Luen Heng ,  Xu Ouyang ,  Yunsheng Song ,  Yun-Yu Wang

发明人： Fook-Luen Heng ,  Xu Ouyang ,  Yunsheng Song ,  Yun-Yu Wang

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F2217/16

摘要： A method of failure detection of an integrated circuit (IC) layout includes determining a critical path distance between a first geometric feature of the IC layout and a second geometric feature of the IC layout; and comparing the determined critical path distance to a defined minimum critical path distance between the first and second geometric features, wherein the defined minimum critical path distance corresponds to a desired electrical property of the IC layout, independent of any geometric-based ground rule minimum distance for the IC layout; identifying any determined critical path distances that are less than the defined minimum critical path distance as a design violation; and modifying the IC layout by eliminating the identified design violations.

摘要翻译： 集成电路（IC）布局的故障检测方法包括确定IC布局的第一几何特征与IC布局的第二几何特征之间的关键路径距离; 以及将所确定的关键路径距离与所述第一和第二几何特征之间的限定的最小关键路径距离进行比较，其中所述限定的最小关键路径距离对应于所述IC布局的所需电气特性，独立于任何基于几何的基准规则最小距离 用于IC布局; 识别小于定义的最小关键路径距离的任何确定的关键路径距离作为设计违规; 并通过消除所识别的设计违规来修改IC布局。

公开(公告)号：US20100318956A1

公开(公告)日：2010-12-16

申请号：US12482504

申请日：2009-06-11

申请人： Geng Han ,  Fook-Luen Heng ,  Jin Fuw Lee ,  Chao Yi Tien ,  Rama N. Singh

发明人： Geng Han ,  Fook-Luen Heng ,  Jin Fuw Lee ,  Chao Yi Tien ,  Rama N. Singh

IPC分类号： G06F17/50

CPC分类号： G03F1/36

摘要： A method of physical design for integrated circuit (IC) chip fabrication, physical design system and program product therefor. A design shape is fragmented into segments for Optical Proximity Correction (OPC) and a harmonic mean of the segments is determined. Electrical intent is determined for the shape and a harmonic mean is determined for the segments. Segments may be moved based on a effect on the harmonic mean from moving the segments, measured using a harmonic mean cost function. Finally segmented shapes are passed to OPC.

摘要翻译： 一种用于集成电路（IC）芯片制造，物理设计系统及其程序产品的物理设计方法。 设计形状被分段为光学邻近校正（OPC）的段，并确定段的谐波平均值。 根据形状确定电气意图，并为段确定谐波平均值。 可以基于使用谐波平均成本函数测量的移动段的对谐波平均值的影响来移动段。 最后分段形状传递给OPC。