公开(公告)号：US07676775B2

公开(公告)日：2010-03-09

申请号：US11754947

申请日：2007-05-29

申请人： Howard Chen ,  Katherine V. Hawkins ,  Fook-Luen Heng ,  Louis Hsu ,  Xu Ouyang

发明人： Howard Chen ,  Katherine V. Hawkins ,  Fook-Luen Heng ,  Louis Hsu ,  Xu Ouyang

IPC分类号： G06F17/50

CPC分类号： G01R31/2894 ,  G01R31/31718 ,  G01R31/318314 ,  G11C29/10 ,  G11C29/56 ,  G11C29/56008

摘要： A method for determining the root causes of fail patterns in integrated circuit chips is provide wherein a known integrated circuit chip layout is used to identify a plurality of potential defects and a plurality of potential fail patterns in the integrated circuit chip. Correlations between the potential defects and the potential fail patterns that result from those defects are identified. Based on this identification, the potential fail patterns are grouped by common potential defect. An actual integrated circuit chip that is manufactured in accordance with the test layout is tested for failure patterns. These failure patterns are then compared to the groupings of potential fail patterns. When a match is found, that is when a given group of fail patterns is found in the actual integrated circuit chip, then the potential defect associated with the potential fail patterns to which the actual fail patterns are matched is identified. This defect is the root cause of the failure pattern in the actual chip.

摘要翻译： 提供了一种用于确定集成电路芯片中的故障模式的根本原因的方法，其中使用已知的集成电路芯片布局来识别集成电路芯片中的多个潜在缺陷和多个潜在故障模式。 鉴定出潜在缺陷与由这些缺陷产生的潜在失效模式之间的相关性。 基于此识别，潜在的故障模式由共同的潜在缺陷分组。 测试根据测试布局制造的实际集成电路芯片的故障模式。 然后将这些故障模式与潜在故障模式的分组进行比较。 当发现匹配时，即在实际的集成电路芯片中发现给定的一组故障模式时，识别与实际故障模式匹配的潜在故障模式相关联的潜在缺陷。 这个缺陷是实际芯片中故障模式的根本原因。

公开(公告)号：US20080301597A1

公开(公告)日：2008-12-04

申请号：US11754947

申请日：2007-05-29

申请人： Howard Chen ,  Katherine V. Hawkins ,  Fook-Luen Heng ,  Louis Hsu ,  Xu Ouyang

发明人： Howard Chen ,  Katherine V. Hawkins ,  Fook-Luen Heng ,  Louis Hsu ,  Xu Ouyang

IPC分类号： G06F17/50

CPC分类号： G01R31/2894 ,  G01R31/31718 ,  G01R31/318314 ,  G11C29/10 ,  G11C29/56 ,  G11C29/56008

摘要： A method for determining the root causes of fail patterns in integrated circuit chips is provide wherein a known integrated circuit chip layout is used to identify a plurality of potential defects and a plurality of potential fail patterns in the integrated circuit chip. Correlations between the potential defects and the potential fail patterns that result from those defects are identified. Based on this identification, the potential fail patterns are grouped by common potential defect. An actual integrated circuit chip that is manufactured in accordance with the test layout is tested for failure patterns. These failure patterns are then compared to the groupings of potential fail patterns. When a match is found, that is when a given group of fail patterns is found in the actual integrated circuit chip, then the potential defect associated with the potential fail patterns to which the actual fail patterns are matched is identified. This defect is the root cause of the failure pattern in the actual chip.

摘要翻译： 提供了一种用于确定集成电路芯片中的故障模式的根本原因的方法，其中使用已知的集成电路芯片布局来识别集成电路芯片中的多个潜在缺陷和多个潜在故障模式。 鉴定出潜在缺陷与由这些缺陷产生的潜在失效模式之间的相关性。 基于此识别，潜在的故障模式由共同的潜在缺陷分组。 测试根据测试布局制造的实际集成电路芯片的故障模式。 然后将这些故障模式与潜在故障模式的分组进行比较。 当发现匹配时，即在实际的集成电路芯片中发现给定的一组故障模式时，识别与实际故障模式匹配的潜在故障模式相关联的潜在缺陷。 这个缺陷是实际芯片中故障模式的根本原因。

公开(公告)号：US08108803B2

公开(公告)日：2012-01-31

申请号：US12603594

申请日：2009-10-22

申请人： Fook-Luen Heng ,  Xu Ouyang ,  Yunsheng Song ,  Yun-Yu Wang

发明人： Fook-Luen Heng ,  Xu Ouyang ,  Yunsheng Song ,  Yun-Yu Wang

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F2217/16

摘要： A method of failure detection of an integrated circuit (IC) layout includes determining a critical path distance between a first geometric feature of the IC layout and a second geometric feature of the IC layout; and comparing the determined critical path distance to a defined minimum critical path distance between the first and second geometric features, wherein the defined minimum critical path distance corresponds to a desired electrical property of the IC layout, independent of any geometric-based ground rule minimum distance for the IC layout; identifying any determined critical path distances that are less than the defined minimum critical path distance as a design violation; and modifying the IC layout by eliminating the identified design violations.

摘要翻译： 集成电路（IC）布局的故障检测方法包括确定IC布局的第一几何特征与IC布局的第二几何特征之间的关键路径距离; 以及将所确定的关键路径距离与所述第一和第二几何特征之间的限定的最小关键路径距离进行比较，其中所述限定的最小关键路径距离对应于所述IC布局的所需电气特性，独立于任何基于几何的基准规则最小距离 用于IC布局; 识别小于定义的最小关键路径距离的任何确定的关键路径距离作为设计违规; 并通过消除所识别的设计违规来修改IC布局。

公开(公告)号：US20110099529A1

公开(公告)日：2011-04-28

申请号：US12603594

申请日：2009-10-22

申请人： Fook-Luen Heng ,  Xu Ouyang ,  Yunsheng Song ,  Yun-Yu Wang

发明人： Fook-Luen Heng ,  Xu Ouyang ,  Yunsheng Song ,  Yun-Yu Wang

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F2217/16

摘要： A method of failure detection of an integrated circuit (IC) layout includes determining a critical path distance between a first geometric feature of the IC layout and a second geometric feature of the IC layout; and comparing the determined critical path distance to a defined minimum critical path distance between the first and second geometric features, wherein the defined minimum critical path distance corresponds to a desired electrical property of the IC layout, independent of any geometric-based ground rule minimum distance for the IC layout; identifying any determined critical path distances that are less than the defined minimum critical path distance as a design violation; and modifying the IC layout by eliminating the identified design violations.

摘要翻译： 集成电路（IC）布局的故障检测方法包括确定IC布局的第一几何特征与IC布局的第二几何特征之间的关键路径距离; 以及将所确定的关键路径距离与所述第一和第二几何特征之间的限定的最小关键路径距离进行比较，其中所述限定的最小关键路径距离对应于所述IC布局的所需电气特性，独立于任何基于几何的基准规则最小距离 用于IC布局; 识别小于定义的最小关键路径距离的任何确定的关键路径距离作为设计违规; 并通过消除所识别的设计违规来修改IC布局。

公开(公告)号：US08742782B2

公开(公告)日：2014-06-03

申请号：US13191555

申请日：2011-07-27

申请人： Xu Ouyang ,  Tso-Hui Ting ,  Ping-Chuan Wang ,  Yongchun Xin

发明人： Xu Ouyang ,  Tso-Hui Ting ,  Ping-Chuan Wang ,  Yongchun Xin

IPC分类号： G01R31/28

CPC分类号： G01R31/31728

摘要： An on-chip technique for noncontact electrical testing of a test structure on a chip is provided. On-chip photodiodes receives pump light from a pump light source, where the on-chip photodiodes are electrically connected to the test structure and are configured to generate power for the test structure. An on-chip coupling unit receives probe light from a probe light source, where the on-chip coupling unit is optically connected to on-chip waveguides through which the probe light is transferred. On-chip switches open in response to receiving voltage output from the test structure, and the on-chip switches remain closed when the voltage output is not received from the test structure. The on-chip switches pass the probe light when opened by the voltage output from the test structure. The on-chip switches block the probe light by remaining closed, when the voltage output is not received from the test structure.

摘要翻译： 提供了芯片上测试结构的非接触电测试的片上技术。 片上光电二极管从泵浦光源接收泵浦光，其中片上光电二极管电连接到测试结构，并且被配置为产生用于测试结构的电力。 片上耦合单元接收来自探针光源的探测光，其中片上耦合单元光学连接到传输探针光的片上波导。 响应于测试结构的接收电压输出，片内开关打开，并且当没有从测试结构接收到电压输出时，片上开关保持闭合。 当由测试结构输出的电压打开时，片上开关通过探测灯。 当没有从测试结构接收到电压输出时，片内开关通过保持关闭来阻止探测光。

公开(公告)号：US08369976B2

公开(公告)日：2013-02-05

申请号：US12144093

申请日：2008-06-23

申请人： Keith Kwong Hon Wong ,  Xu Ouyang ,  Yunsheng Song

发明人： Keith Kwong Hon Wong ,  Xu Ouyang ,  Yunsheng Song

IPC分类号： G06F19/00

CPC分类号： H01L22/20 ,  H01L22/12

摘要： A method for increasing overall yield in semiconductor manufacturing including routing wafers or wafer lots from tool to tool in a manner which at least partially neutralizes or compensates for processing variations. A system for increasing overall yield in semiconductor manufacturing includes a module for recording processing data from plural first and second types of tools and a module for routing wafers or wafer lots from tools of the first type of tools to tools of the second type of tools so as to at least partially neutralizes or compensate for processing variation.

摘要翻译： 一种用于提高半导体制造中的总产量的方法，包括以至少部分中和或补偿处理变化的方式从工具到工具路由晶圆或晶片批次。 用于提高半导体制造中的整体产量的系统包括用于记录来自多个第一和第二类型工具的处理数据的模块和用于将晶片或晶片批次从第一类型工具的工具转移到第二类型工具的工具的模块， 至少部分地中和或补偿处理变化。

公开(公告)号：US20120188002A1

公开(公告)日：2012-07-26

申请号：US13438230

申请日：2012-04-03

申请人： Louis L. Hsu ,  Xu Ouyang ,  Chih-Chao Yang

发明人： Louis L. Hsu ,  Xu Ouyang ,  Chih-Chao Yang

IPC分类号： H03K17/687 ,  H01L21/02

CPC分类号： H01L28/40 ,  H01L22/14 ,  H01L22/22 ,  H01L22/34 ,  H01L23/5223 ,  H01L27/0688 ,  H01L27/0805 ,  H01L28/60 ,  H01L2924/0002 ,  Y10T307/865 ,  H01L2924/00

摘要： A modularized capacitor array includes a plurality of capacitor modules. Each capacitor module includes a capacitor and a switching device that is configured to electrically disconnect the capacitor. The switching device includes a sensing unit configured to detect the level of leakage of the capacitor so that the switching device disconnects the capacitor electrically if the leakage current exceeds a predetermined level. Each capacitor module can include a single capacitor plate, two capacitor plates, or more than two capacitor plates. The leakage sensors and switching devices are employed to electrically disconnect any capacitor module of the capacitor array that becomes leaky, thereby protecting the capacitor array from excessive electrical leakage.

摘要翻译： 模块化电容器阵列包括多个电容器模块。 每个电容器模块包括电容器和被配置为电气断开电容器的开关装置。 开关装置包括：感测单元，被配置为检测电容器的泄漏电平，使得如果泄漏电流超过预定电平，则开关装置电连接电容器。 每个电容器模块可以包括单个电容器板，两个电容器板或多于两个的电容器板。 泄漏传感器和开关装置用于电气断开任何电容器阵列的电容器模块，从而保护电容器阵列免于漏电。

公开(公告)号：US20110069425A1

公开(公告)日：2011-03-24

申请号：US12565802

申请日：2009-09-24

申请人： Louis L. Hsu ,  Xu Ouyang ,  Chih-Chao Yang

发明人： Louis L. Hsu ,  Xu Ouyang ,  Chih-Chao Yang

IPC分类号： H01G4/38 ,  H01L21/02 ,  H03K17/687

CPC分类号： H01L28/40 ,  H01L22/14 ,  H01L22/22 ,  H01L22/34 ,  H01L23/5223 ,  H01L27/0688 ,  H01L27/0805 ,  H01L28/60 ,  H01L2924/0002 ,  Y10T307/865 ,  H01L2924/00

摘要： A modularized capacitor array includes a plurality of capacitor modules. Each capacitor module includes a capacitor and a switching device that is configured to electrically disconnect the capacitor. The switching device includes a sensing unit configured to detect the level of leakage of the capacitor so that the switching device disconnects the capacitor electrically if the leakage current exceeds a predetermined level. Each capacitor module can include a single capacitor plate, two capacitor plates, or more than two capacitor plates. The leakage sensors and switching devices are employed to electrically disconnect any capacitor module of the capacitor array that becomes leaky, thereby protecting the capacitor array from excessive electrical leakage.

摘要翻译： 模块化电容器阵列包括多个电容器模块。 每个电容器模块包括电容器和被配置为电气断开电容器的开关装置。 开关装置包括：感测单元，被配置为检测电容器的泄漏电平，使得如果泄漏电流超过预定电平，则开关装置电连接电容器。 每个电容器模块可以包括单个电容器板，两个电容器板或多于两个的电容器板。 泄漏传感器和开关装置用于电气断开任何电容器阵列的电容器模块，从而保护电容器阵列免于漏电。

公开(公告)号：US07682842B2

公开(公告)日：2010-03-23

申请号：US12129712

申请日：2008-05-30

申请人： Rao H. Desineni ,  Xu Ouyang ,  Hargurpreet Singh ,  Yunsheng Song ,  Stephen Wu

发明人： Rao H. Desineni ,  Xu Ouyang ,  Hargurpreet Singh ,  Yunsheng Song ,  Stephen Wu

IPC分类号： H01L21/00

CPC分类号： G01R31/2894

摘要： A method for identifying potentially defective integrated circuit chips and excluding them from future testing as wafers move through a manufacturing line The method includes data-collecting steps, tagging the chips on wafers identified as potentially bad chips based on information collected as the wafer moves down the fabrication line, evaluating test cost savings by eliminating any further tests on the tagged chips preferably using a test cost database. Considering all the future tests to be preformed, the tagged chips are skipped if it is determined that the test cost saving is significant. Tagging bad chips is based on various criteria and models which are dynamically adjusted by performing the wafer final test on samples of the tagged chips and feeding-back the final test results. The dynamic adaptive adjustment method preferably includes a feedback loop or iterative process to evaluate financial tradeoffs when assessing the profit of salvaging chips against the additional test costs.

摘要翻译： 一种用于识别潜在有缺陷的集成电路芯片的方法，并将其从将来的测试中排除，因为晶片移动通过生产线。该方法包括数据收集步骤，基于当晶片向下移动时收集的信息将标记为潜在的坏芯片的晶片上的芯片标记 通过消除对标记芯片的任何进一步测试，优选使用测试成本数据库来评估测试成本节省。 考虑到将要执行的所有将来的测试，如果确定测试成本节省是重要的，则标记的芯片被跳过。 标记坏芯片是基于各种标准和模型，通过对标记芯片的样品进行晶圆最终测试并反馈最终测试结果来动态调整。 动态自适应调整方法优选地包括反馈循环或迭代过程，以在评估补救筹码的利润与额外的测试成本时评估金融权衡。

公开(公告)号：US20090175068A1

公开(公告)日：2009-07-09

申请号：US11969981

申请日：2008-01-07

申请人： Xu Ouyang ,  Louis C. Hsu

发明人： Xu Ouyang ,  Louis C. Hsu

IPC分类号： G11C11/00

CPC分类号： G11C11/412

摘要： An SRAM device comprising a pair of MCSFETs connected as access transistors (pass gates). An SRAM device design structure embodied or stored in a machine readable medium includes two MCSFETs connected as access transistors.

摘要翻译： 一种SRAM器件，包括连接作为存取晶体管（通孔）的一对MCSFET。 体现或存储在机器可读介质中的SRAM器件设计结构包括作为存取晶体管连接的两个MCSFET。