公开(公告)号：US07750393B2

公开(公告)日：2010-07-06

申请号：US11987008

申请日：2007-11-26

申请人： Won-joo Kim ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim

发明人： Won-joo Kim ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim

IPC分类号： H01L29/788 ,  H01L29/792

CPC分类号： H01L29/7885 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42336 ,  H01L29/42344 ,  H01L29/42352 ,  H01L29/7887 ,  H01L29/792 ,  H01L29/7923

摘要： Provided are example embodiments of a non-volatile memory device and a method of fabricating the same. The non-volatile memory device may include a control gate electrode arranged on a semiconductor substrate, a gate insulating layer interposed between the semiconductor substrate and the control gate electrode, a storage node layer interposed between the gate insulating layer and the control gate electrode, a blocking insulating layer interposed between the storage node layer and the control gate electrode, first dopant doping regions along a first side of the control gate electrode, and second dopant doping regions along a second side of the control gate electrode. The first dopant doping regions may alternate with the second dopant doping regions. Stated differently, each of the second dopant doping regions may be arranged in a region on the second side of the control gate electrode that is adjacent to one of the first dopant doping regions.

摘要翻译： 提供了非易失性存储器件的示例性实施例及其制造方法。 非易失性存储器件可以包括布置在半导体衬底上的控制栅电极，介于半导体衬底和控制栅电极之间的栅极绝缘层，介于栅极绝缘层和控制栅电极之间的存储节点层， 插入在所述存储节点层和所述控制栅电极之间的阻挡绝缘层，沿着所述控制栅电极的第一侧的第一掺杂剂掺杂区域和沿着所述控制栅电极的第二侧的第二掺杂剂掺杂区域。 第一掺杂剂掺杂区域可以与第二掺杂剂掺杂区域交替。 换句话说，每个第二掺杂剂掺杂区域可以被布置在与第一掺杂剂掺杂区域中的一个相邻的控制栅电极的第二侧上的区域中。

公开(公告)号：US20100072452A1

公开(公告)日：2010-03-25

申请号：US12585582

申请日：2009-09-18

申请人： Suk-pil Kim ,  June-mo Koo ,  Tae-eung Yoon

发明人： Suk-pil Kim ,  June-mo Koo ,  Tae-eung Yoon

IPC分类号： H01L45/00

CPC分类号： H01L45/04 ,  H01L27/2409 ,  H01L27/249 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/146

摘要： Provided is a non-volatile memory device having a stacked structure that is easily highly integrated and a method of economically fabricating the non-volatile memory device. The non-volatile memory device may include at least one first electrode and at least one second electrode that cross each other. At least one data storage layer may be disposed on a section where the at least one first electrode and the at least one second electrode cross each other. The at least one first electrode may include a first conductive layer and a first semiconductor layer.

摘要翻译： 提供了具有容易高度集成的堆叠结构的非易失性存储器件以及经济地制造非易失性存储器件的方法。 非易失性存储器件可以包括至少一个第一电极和至少一个彼此交叉的第二电极。 至少一个数据存储层可以设置在至少一个第一电极和至少一个第二电极彼此交叉的部分上。 所述至少一个第一电极可以包括第一导电层和第一半导体层。

公开(公告)号：US20090122613A1

公开(公告)日：2009-05-14

申请号：US12149213

申请日：2008-04-29

申请人： Won-joo Kim ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim ,  Tae-eung Yoon ,  Tae-hee Lee

发明人： Won-joo Kim ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim ,  Tae-eung Yoon ,  Tae-hee Lee

IPC分类号： G11C16/06 ,  G11C11/34

CPC分类号： G11C16/10 ,  G11C2213/71

摘要： A non-volatile memory device may include a plurality of stacked semiconductor layers, a plurality of NAND strings, a common bit line, a common source line, and/or a plurality of string selection lines. The plurality of NAND strings may be on the plurality of semiconductor layers. Each of the plurality of NAND strings may include a plurality of memory cells and/or at least one string selection transistor arranged in a NAND-cell array. The common bit line may be commonly connected to each of the NAND strings at a first end of the memory cells. The common source line may be commonly connected to each of the NAND strings at a second end of the memory cells. The plurality of string selection lines may be coupled to the at least one string selection transistor included in each of the NAND strings such that a signal applied to the common bit line is selectively applied to the NAND strings.

摘要翻译： 非易失性存储器件可以包括多个堆叠半导体层，多个NAND串，公共位线，公共源极线和/或多个串选择线。 多个NAND串可以在多个半导体层上。 多个NAND串中的每一个可以包括布置在NAND单元阵列中的多个存储单元和/或至少一个串选择晶体管。 公共位线可以在存储器单元的第一端处共同连接到每个NAND串。 公共源极线可以在存储器单元的第二端处共同连接到每个NAND串。 多个串选择线可以耦合到包括在每个NAND串中的至少一个串选择晶体管，使得施加到公共位线的信号被选择性地施加到NAND串。

公开(公告)号：US20080191264A1

公开(公告)日：2008-08-14

申请号：US12010139

申请日：2008-01-22

申请人： Won-Joo Kim ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim ,  Tae-hee Lee

发明人： Won-Joo Kim ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim ,  Tae-hee Lee

IPC分类号： H01L29/00 ,  H01L21/3205

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： Non-volatile memory devices highly integrated using an oxide based compound semiconductor and methods of operating and fabricating the same are provided. A non-volatile memory device may include one or more oxide based compound semiconductor layers. A plurality of auxiliary gate electrodes may be arranged to be insulated from the one or more oxide based compound semiconductor layers. A plurality of control gate electrodes may be positioned between adjacent pairs of the plurality of auxiliary gate electrodes at a different level from the plurality of auxiliary gate electrodes. The plurality of control gate electrodes may be insulated from the one or more oxide based compound semiconductor layers. A plurality of charge storing layers may be interposed between the one or more oxide based compound semiconductor layers and the plurality of control gate electrodes.

摘要翻译： 提供了使用基于氧化物的化合物半导体高度集成的非易失性存储器件及其操作和制造方法。 非易失性存储器件可以包括一个或多个基于氧化物的化合物半导体层。 多个辅助栅极电极可以布置成与一个或多个氧化物基化合物半导体层绝缘。 多个控制栅电极可以位于与多个辅助栅极电极不同的多个辅助栅电极的相邻对之间。 多个控制栅电极可以与一个或多个氧化物基化合物半导体层绝缘。 可以在一个或多个氧化物基化合物半导体层和多个控制栅电极之间插入多个电荷存储层。

公开(公告)号：US20080025106A1

公开(公告)日：2008-01-31

申请号：US11715404

申请日：2007-03-08

申请人： Won-joo Kim ,  Suk-pil Kim ,  Jae-woong Hyun ,  Yoon-dong Park ,  June-mo Koo

发明人： Won-joo Kim ,  Suk-pil Kim ,  Jae-woong Hyun ,  Yoon-dong Park ,  June-mo Koo

IPC分类号： G11C11/34

CPC分类号： G11C16/0433 ,  G11C16/0491 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

摘要： Unit cells of a non-volatile memory device and a method thereof are provided. In an example, the unit cell may include a first memory transistor and a second memory transistor connected to each other in series and further connected in common to a word line, the first and second memory transistors including first and second storage nodes, respectively, the first and second storage nodes configured to execute concurrent memory operations. In another example, the unit cell may include a semiconductor substrate in which first and second bit line regions are defined. first and second storage node layers respectively formed on the semiconductor substrate between the first and second bit line regions, a first pass gate electrode formed on the semiconductor substrate between the first bit line region and the first storage node layer, a second pass gate electrode formed on the semiconductor substrate between the second bit line region and the second storage node layer, a third pass gate electrode formed on the semiconductor substrate between the first and second storage node layers, a third bit line region formed in a portion of the semiconductor substrate under the third pass gate electrode and a control gate electrode extending across the first and second storage node layers. The example unit cells may be implemented within a non-volatile memory device (e.g., a flash memory device), such that the non-volatile memory device may include a plurality of example unit cells.

摘要翻译： 提供非易失性存储器件的单元电池及其方法。 在一个示例中，单元可以包括串联连接并进一步连接到字线的第一存储晶体管和第二存储晶体管，第一和第二存储晶体管分别包括第一和第二存储节点， 配置为执行并发存储器操作的第一和第二存储节点。 在另一示例中，单元可以包括其中限定了第一和第二位线区域的半导体衬底。 分别形成在第一和第二位线区域之间的半导体衬底上的第一和第二存储节点层，形成在第一位线区域和第一存储节点层之间的半导体衬底上的第一遍栅极电极，形成的第二遍栅极电极 在第二位线区域和第二存储节点层之间的半导体衬底上，形成在第一和第二存储节点层之间的半导体衬底上的第三遍栅极电极，形成在半导体衬底的一部分中的第三位线区域 所述第三通道栅极电极和跨越所述第一和第二存储节点层延伸的控制栅极电极。 示例性单元单元可以在非易失性存储器件（例如，闪存器件）内实现，使得非易失性存储器件可以包括多个示例单位单元。

公开(公告)号：US20080023749A1

公开(公告)日：2008-01-31

申请号：US11724290

申请日：2007-03-15

申请人： Won-joo Kim ,  Suk-pil Kim ,  Yoon-dong Park ,  June-mo Koo

发明人： Won-joo Kim ,  Suk-pil Kim ,  Yoon-dong Park ,  June-mo Koo

IPC分类号： H01L29/788 ,  G11C5/14 ,  H01L21/336

CPC分类号： H01L29/42352 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42336

摘要： Example embodiments provide a non-volatile memory device with increased integration and methods of operating and fabricating the same. A non-volatile memory device may include a plurality of first storage node films and a plurality of first control gate electrodes on a semiconductor substrate. A plurality of second storage node films and a plurality of second control gate electrodes may be recessed into the semiconductor substrate between two adjacent first control gate electrodes and below the bottom of the plurality of first control gate electrodes. A plurality of bit line regions may be on the semiconductor substrate and each may extend across the plurality of first control gate electrodes and the plurality of second control gate electrodes.

摘要翻译： 示例性实施例提供了具有增加的集成的非易失性存储器件及其操作和制造方法。 非易失性存储器件可以包括多个第一存储节点膜和半导体衬底上的多个第一控制栅电极。 多个第二存储节点膜和多个第二控制栅电极可以凹入到两个相邻的第一控制栅电极之间并且在多个第一控制栅电极的底部之下的半导体衬底中。 多个位线区域可以在半导体衬底上，并且每个可以跨越多个第一控制栅极电极和多个第二控制栅电极延伸。

公开(公告)号：US08299520B2

公开(公告)日：2012-10-30

申请号：US12544631

申请日：2009-08-20

申请人： Suk-pil Kim ,  Yoon-dong Park ,  Jae-young Choi ,  June-mo Koo ,  Byung-hee Hong

发明人： Suk-pil Kim ,  Yoon-dong Park ,  Jae-young Choi ,  June-mo Koo ,  Byung-hee Hong

IPC分类号： H01L29/66 ,  H01L29/788 ,  G11C16/04

CPC分类号： H01L29/66833 ,  B82Y10/00 ,  G11C16/0483 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/792

摘要： According to some embodiments, a semiconductor device includes first and second auxiliary gate electrodes and a semiconductor layer crossing the first and second auxiliary gate electrodes. A primary gate electrode is provided on the semiconductor layer so that the semiconductor layer is between the primary gate electrode and the first and second auxiliary gate electrodes. Moreover, the first and second auxiliary gate electrodes are configured to induce respective first and second field effect type source/drain regions in the semiconductor layer. Related methods are also discussed.

摘要翻译： 根据一些实施例，半导体器件包括第一和第二辅助栅电极以及与第一和第二辅助栅电极交叉的半导体层。 主栅电极设置在半导体层上，使得半导体层位于主栅电极和第一和第二辅助栅电极之间。 此外，第一和第二辅助栅电极被配置为在半导体层中诱发相应的第一和第二场效应源极/漏极区。 还讨论了相关方法。

公开(公告)号：US08124968B2

公开(公告)日：2012-02-28

申请号：US12366151

申请日：2009-02-05

申请人： June-mo Koo ,  Suk-pil Kim ,  Tae-Eung Yoon

发明人： June-mo Koo ,  Suk-pil Kim ,  Tae-Eung Yoon

IPC分类号： H01L29/08

CPC分类号： H01L27/1021 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/146

摘要： Provided are a non-volatile memory device which can be extended in a stack structure and thus can be highly integrated, and a method of manufacturing the non-volatile memory device. The non-volatile memory device includes: at least one first electrode, at least one second electrode crossing the at least one first electrode, at least one data storing layer interposed between the at least one first electrode and the second electrode, at a region in which the at least one first electrode crosses the at least one second electrode and at least one metal silicide layer interposed between the at least one first electrode and the at least one second electrode, at the region in which the at least one first electrode crosses the at least one second electrode.

摘要翻译： 提供了可以以堆叠结构进行扩展并因此可以高度集成的非易失性存储器件，以及制造非易失性存储器件的方法。 所述非易失性存储器件包括：至少一个第一电极，至少一个第二电极，与所述至少一个第一电极交叉，至少一个数据存储层插入在所述至少一个第一电极和所述第二电极之间的区域中 所述至少一个第一电极与所述至少一个第二电极交叉，并且所述至少一个金属硅化物层插入在所述至少一个第一电极和所述至少一个第二电极之间，所述至少一个第一电极在所述至少一个第一电极与 至少一个第二电极。

公开(公告)号：US07796432B2

公开(公告)日：2010-09-14

申请号：US12149213

申请日：2008-04-29

申请人： Won-joo Kim ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim ,  Tae-eung Yoon ,  Tae-hee Lee

发明人： Won-joo Kim ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim ,  Tae-eung Yoon ,  Tae-hee Lee

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C2213/71

摘要： A non-volatile memory device may include a plurality of stacked semiconductor layers, a plurality of NAND strings, a common bit line, a common source line, and/or a plurality of string selection lines. The plurality of NAND strings may be on the plurality of semiconductor layers. Each of the plurality of NAND strings may include a plurality of memory cells and/or at least one string selection transistor arranged in a NAND-cell array. The common bit line may be commonly connected to each of the NAND strings at a first end of the memory cells. The common source line may be commonly connected to each of the NAND strings at a second end of the memory cells. The plurality of string selection lines may be coupled to the at least one string selection transistor included in each of the NAND strings such that a signal applied to the common bit line is selectively applied to the NAND strings.

摘要翻译： 非易失性存储器件可以包括多个堆叠半导体层，多个NAND串，公共位线，公共源极线和/或多个串选择线。 多个NAND串可以在多个半导体层上。 多个NAND串中的每一个可以包括布置在NAND单元阵列中的多个存储单元和/或至少一个串选择晶体管。 公共位线可以在存储器单元的第一端处共同连接到每个NAND串。 公共源极线可以在存储器单元的第二端处共同连接到每个NAND串。 多个串选择线可以耦合到包括在每个NAND串中的至少一个串选择晶体管，使得施加到公共位线的信号被选择性地施加到NAND串。

公开(公告)号：US20090261314A1

公开(公告)日：2009-10-22

申请号：US12232745

申请日：2008-09-23

申请人： Suk-pil Kim ,  Yoon-dong Park ,  June-mo Koo

发明人： Suk-pil Kim ,  Yoon-dong Park ,  June-mo Koo

IPC分类号： H01L45/00

CPC分类号： H01L27/249 ,  H01L27/2409 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/146

摘要： Provided are a non-volatile memory device that may be configured in a stacked structure and may be more easily highly integrated, and a method of fabricating the non-volatile memory device. At least one first electrode and at least one second electrode are provided. The at least one second electrode may cross the at least one first electrode. At least one data storage layer may be at an intersection between the at least one first electrode and the at least one second electrode. Any one of the at least one first electrode and the at least one second electrode may include at least one junction diode connected to the at least one data storage layer.

摘要翻译： 提供了可以被配置为堆叠结构并且可以更容易地高度集成的非易失性存储器件，以及制造非易失性存储器件的方法。 提供至少一个第一电极和至少一个第二电极。 所述至少一个第二电极可以穿过所述至少一个第一电极。 至少一个数据存储层可以在至少一个第一电极和至少一个第二电极之间的交叉点处。 所述至少一个第一电极和所述至少一个第二电极中的任何一个可以包括连接到所述至少一个数据存储层的至少一个结二极管。