Dope Filtering Method and Solution Casting Method Using The Dope
    41.
    发明申请
    Dope Filtering Method and Solution Casting Method Using The Dope 审中-公开
    涂料过滤方法和溶液浇铸方法

    公开(公告)号:US20080073810A1

    公开(公告)日:2008-03-27

    申请号:US11663183

    申请日:2005-09-20

    摘要: A dope (36) containing TAC and plasticizer is produced. Foreign materials in the dope (36) are filtrated by a filtration device (57). In the filtration device (57), the dope (36) flows from an outer passage (58a) to an inner passage (58b) through a filter (59). The filter (59) has a first layer (59a), a second layer (59b), and a third layer (59c), which are formed of sintered metal fibers. An average diameter of the sintered metal fibers of the first layer (59a) is 8 mm, that of the second layer (59b) is 4 mm, and that of the third layer (59c) is 20 mm. The filter (59) is roasted 2 hours at 400° C. and reused. Breakages from the sintered metal fibers in the first and second layers (59a, 59b) are filtrated in the third layer (59c).

    摘要翻译: 制备含有TAC和增塑剂的涂料(36)。 涂料(36)中的异物用过滤装置(57)过滤。 在过滤装置(57)中,涂料(36)通过过滤器(59)从外部通道(58a)流向内部通道(58b)。 过滤器(59)具有由烧结金属纤维形成的第一层(59a),第二层(59b)和第三层(59c)。 第一层(59a)的烧结金属纤维的平均直径为8mm,第二层(59b)的平均直径为4mm,第三层(59c)的平均直径为20mm。 过滤器(59)在400℃下烘烤2小时并重新使用。 第一层和第二层(59a,59b)中的烧结金属纤维的断裂在第三层(59c)中被过滤。

    Magnetic head and method of manufacturing the same
    42.
    发明申请
    Magnetic head and method of manufacturing the same 审中-公开
    磁头及其制造方法

    公开(公告)号:US20070278217A1

    公开(公告)日:2007-12-06

    申请号:US11634534

    申请日:2006-12-06

    IPC分类号: H05B6/10

    CPC分类号: G11B5/127

    摘要: There is provided a magnetic head where a heater is reliably incorporated into the magnetic head and the fly height of the magnetic head above a medium surface can be reliably controlled using thermal expansion due to heat from the heater. A method of manufacturing the magnetic head is also provided. The method of manufacturing includes, as steps of manufacturing the heater, a step of forming a silicon dioxide layer on the surface of a substrate, a step of forming, as heater forming layers, a tantalum layer, a heating layer, and another tantalum layer in that order on the surface of the silicon dioxide layer, a step of patterning a resist in accordance with a planar pattern of the heater to cover the surface of the heater forming layers, a step of forming the heater in a pattern by carrying out ion milling on the heater forming layers with the resist as a mask, a step of sputtering a silicon dioxide layer with a greater thickness than a thickness of the heater in a state where the surface of the heater has been covered with the resist, and a step of removing the resist together with the silicon dioxide layer that covers an outer surface of the resist from the surface of the heater by lifting off.

    摘要翻译: 提供了一种磁头,其中加热器可靠地结合到磁头中,并且可以通过来自加热器的热量的热膨胀可靠地控制磁介质表面上方的磁头的飞行高度。 还提供了一种制造磁头的方法。 制造方法包括作为制造加热器的步骤,在基板的表面上形成二氧化硅层的步骤,形成作为加热器形成层的钽层,加热层和另一钽层的步骤 按照该二氧化硅层表面的顺序,根据加热器的平面图案图案化抗蚀剂以覆盖加热器形成层的表面的步骤,通过进行离子形成图案的加热器的步骤 在抗蚀剂作为掩模的加热器形成层上进行研磨,在加热器的表面被抗蚀剂覆盖的状态下溅射厚度大于加热器的厚度的二氧化硅层的步骤,以及步骤 通过剥离从加热器的表面覆盖抗蚀剂的外表面的二氧化硅层一起除去抗蚀剂。

    Method of erasing data in non-volatile semiconductor memory device while suppressing variation
    43.
    发明申请
    Method of erasing data in non-volatile semiconductor memory device while suppressing variation 有权
    在抑制变化的同时擦除非易失性半导体存储器件中的数据的方法

    公开(公告)号:US20070242519A1

    公开(公告)日:2007-10-18

    申请号:US11812704

    申请日:2007-06-21

    IPC分类号: G11C16/34

    摘要: According to a method of erasing data in a non-volatile semiconductor memory device, block-round type overerase verify is performed. Specifically, overerase verify and write back are performed sequentially from a first address to a last address. That is, even when a write back pulse is applied after a certain address is selected and verify is performed, address increment from one address to another is performed, regardless of whether verify has been performed or not. Therefore, it is not that the same address is cumulatively rewritten, but write back to a memory cell corresponding to a defective address is sequentially and gradually performed. Accordingly, as write to a memory cell in an overerased state can evenly be performed, influence by off-leakage is suppressed, and a memory cell having threshold voltage distribution with less variation can be implemented.

    摘要翻译: 根据擦除非易失性半导体存储器件中的数据的方法,执行块式过程验证。 具体来说,过度验证和回写是从第一个地址到最后一个地址顺序执行的。 也就是说,即使在选择了某个地址并进行验证之后应用写回脉冲的情况下,执行从一个地址到另一个地址的地址增量,而不管是否执行了验证。 因此,不是相同的地址被累积地重写,而是顺序地逐渐执行写入与缺陷地址对应的存储单元。 因此,能够均匀地进行对高电平状态的存储单元的写入,能够抑制泄漏的影响,能够实现具有小变化的阈值电压分布的存储单元。

    Method of forming a conductive pattern
    44.
    发明申请
    Method of forming a conductive pattern 失效
    形成导电图案的方法

    公开(公告)号:US20070221612A1

    公开(公告)日:2007-09-27

    申请号:US11482467

    申请日:2006-07-07

    IPC分类号: B44C1/22 C23F1/00

    摘要: A method of forming a conductive pattern can form a conductive pattern where the aspect ratio of the height to the width is high with favorable electrical connectivity. The method includes a process that forms a first resist layer, which exposes formation positions of a conductive pattern, on a formation surface on which the conductive pattern is to be formed, a process that forms a first stage conductive pattern by carrying out plating at the positions exposed from the first resist layer, a process that forms a first stage protective film which protects the first stage conductive pattern, a process that grinds flat a surface of the first stage protective film and end surfaces of the first stage conductive pattern, a process that forms a second resist layer, which exposes parts of the end surfaces of the first stage conductive pattern more narrowly than the first stage conductive pattern, on the surface of the first stage protective film and the end surfaces of the first stage conductive pattern, and a process that forms a second stage conductive pattern by carrying out plating at the positions on the end surfaces of the first stage conductive pattern that are exposed from the second resist layer.

    摘要翻译: 形成导电图案的方法可以形成导电图案,其中高度与宽度的纵横比高,并且具有良好的电连接性。 该方法包括在形成导电图案的形成表面上形成暴露导电图案的形成位置的第一抗蚀剂层的工艺,通过在其上进行电镀形成第一级导电图案的工艺 从第一抗蚀剂层暴露的位置,形成保护第一级导电图案的第一级保护膜的工艺,研磨第一级保护膜的表面和第一级导电图案的端面的工艺, 其形成第二抗蚀剂层,其在第一级保护膜的表面和第一级导电图案的端面上暴露出比第一级导电图案更窄的第一级导电图案的端面的一部分,并且 通过在第一级导电图案的端面上的位置进行电镀而形成第二级导电图案的工序 其从第二抗蚀剂层暴露。

    Numeric control method and numeric control system
    46.
    发明授权
    Numeric control method and numeric control system 有权
    数控系统和数控系统

    公开(公告)号:US07155303B2

    公开(公告)日:2006-12-26

    申请号:US10504027

    申请日:2002-02-07

    IPC分类号: G06F19/00 G05B13/02 G05B19/42

    摘要: A numerical control system comprises a high speed operation buffer 27 for storing all the NC control data (interpolation movement amount or acceleration or deceleration data, etc.) occurring in time series by executing apart program, a time series data parallel display part 62 for reading and displaying the data in time series, an optimization processing part 61 for making the edit process such as recalculation process to deletion of Null data, etc. and temporally shift the group of specific data or change the pattern in the group of said data, and a second high speed operation buffer 60 for storing the processing result. The series of processes are performed by a personal computer (PC) 51 connected to an NC apparatus 1 to be able to exchange data. The data stored in the second high speed operation buffer 60 is transferred to the side of the NC apparatus 1, and read and executed, whereby the optimal processing with temporal editing is performed at high speed.

    摘要翻译: 数字控制系统包括:高速运算缓冲器27,用于通过执行分开的程序来存储以时间序列出现的所有NC控制数据(插补移动量或加速或减速数据等),用于读取的时间序列数据并行显示部分62 并且以时间序列显示数据;优化处理部分61,用于进行编辑处理如重新计算处理以删除空数据等,并且暂时移动特定数据组或改变所述数据组中的模式;以及 用于存储处理结果的第二高速操作缓冲器60。 一系列处理由连接到NC设备1的个人计算机(PC)51执行以能够交换数据。 存储在第二高速运算缓冲器60中的数据被传送到NC装置1的一侧,并被读取和执行,由此以高速执行具有时间编辑的最佳处理。

    Polishing composition and polishing method using same
    47.
    发明申请
    Polishing composition and polishing method using same 审中-公开
    抛光组合物和抛光方法使用相同

    公开(公告)号:US20060258267A1

    公开(公告)日:2006-11-16

    申请号:US10569906

    申请日:2004-08-27

    摘要: A polishing composition of the present invention contains cerium oxide abrasive grains with surfaces having an adsorption layer formed by adsorption of silicon oxide fine grains. The polishing composition is used in an application for polishing a polishing subject including a laminated body and a silicon oxide film arranged on the laminated body. The laminated body has a semiconductor substrate formed from a monocrystalline silicon or a polycrystalline silicon, a silicon nitride film arranged on the semiconductor substrate, and a surface with grooves. The polishing composition removes a portion of the silicon oxide film located outside the groove.

    摘要翻译: 本发明的研磨用组合物含有具有通过吸附氧化硅细粒而形成的吸附层的表面的氧化铈磨粒。 抛光组合物用于抛光包括层压体的抛光对象和布置在层叠体上的氧化硅膜的应用中。 层叠体具有由单晶硅或多晶硅形成的半导体基板,配置在半导体基板上的氮化硅膜和具有槽的表面。 抛光组合物除去位于凹槽外部的氧化硅膜的一部分。

    Smoothing of dispositions of lattice points for creation of profile

    公开(公告)号:US20060176529A1

    公开(公告)日:2006-08-10

    申请号:US11329310

    申请日:2006-01-09

    IPC分类号: G03F3/08

    CPC分类号: H04N1/6033

    摘要: In order to create a profile that associates lattice points defined in an equipment-dependent color space with lattice points defined in an equipment-independent color space, a reference profile that associates a plurality of lattice points in the equipment-dependent color space with lattice points in the equipment-independent color space is retrieved. A virtual force that acts on a focused lattice point in the equipment-independent color space is defined, and a position at which the focused lattice point is located in a steady-state in which the virtual force acts on the focused lattice point is calculated. The reference profile is referenced in order to retrieve a lattice point in the equipment-dependent color space associated with the position of the steady-state focused lattice point. A profile is created by associating the position of each steady-state focused lattice point with a lattice point in the equipment-dependent color space.

    Method and device for judging the condition of secondary batteries and method for regenerating secondary batteries

    公开(公告)号:US07075305B2

    公开(公告)日:2006-07-11

    申请号:US11129493

    申请日:2005-05-16

    IPC分类号: G01N27/416

    摘要: The internal resistance related value which is related to the internal resistance of a secondary battery is compared with a previously obtained relation between the internal resistance related value and battery condition to judge the battery condition of the secondary battery. Since the internal resistance related value is a value related to the internal resistance which closely depends on the battery condition, the battery condition can be judged in detail based on the above relation. And the internal resistance related value can be obtained more speedily with a predetermined method. On the other hand, when the level of the degradation of a negative electrode is low, an electrolyte is supplemented, and when the level of the degradation of the negative electrode is high, a reducing agent is added to the electrolyte to regenerate the secondary battery. With this regenerating method, the performance of the negative electrode can be recovered without degrading a positive electrode.

    Electronic apparatus and design method
    50.
    发明授权
    Electronic apparatus and design method 有权
    电子设备及设计方法

    公开(公告)号:US07050769B2

    公开(公告)日:2006-05-23

    申请号:US10170375

    申请日:2002-06-14

    IPC分类号: H04B1/04

    摘要: The invention realizes a wireless communication module that is capable of transmitting the fundamental wave with low loss and reducing the double higher harmonic wave level to a desired level or lower as the whole module. The invention provides a front end module to be used for a wireless communication system such as cellular phone in which at least an output power amplifier, a matching circuit, and a low-pass filter are mounted on one insulating substrate and these circuits are connected in the above-mentioned order, wherein the relative phase of the double higher harmonic wave impedance between phases in view of the matching circuit side and the low-pass filter side from the connection point between the matching circuit and the low-pass filter is set in a range of 180 degrees ±90 degrees.

    摘要翻译: 本发明实现了一种无线通信模块,其能够以低损耗发送基波,并将整个模块的双倍高次谐波水平降低到期望水平或更低。 本发明提供一种前端模块,用于无线通信系统,例如蜂窝电话,其中至少一个输出功率放大器,匹配电路和低通滤波器安装在一个绝缘基板上,这些电路连接在 上述顺序,其中从匹配电路和低通滤波器之间的连接点考虑到匹配电路侧和低通滤波器侧的相位之间的双重高次谐波阻抗的相对相位设置在 范围为180度±90度。