摘要:
An input data synchronizing circuit of the invention has a synchronous control counter. Part of count value of the synchronous control counter is supplied to a count register. The count register accesses a parameter ROM utilizing, as part of an address, a count value (phase status) during the input of current data and a count value (phase status) during input of immediately preceding data. The parameter ROM outputs a correction value as an initial value for the synchronous control counter so that the synchronous control counter would output a WINDOW signal synchronous with the input data near the center of the pulse width of the WINDOW signal. The circuit of the invention further includes a rotation correction register which holds stationary time shift information serially input by the rotational errors of the floppy disk drives and which outputs the information to the parameter ROM as part of the address.
摘要:
A colored light generating element can be configured to, while in an active state, pulse between an off state and an on state. A substantially constant offset voltage or current can be applied to the colored light generating element during a predetermined time interval when the light generating element is in the off state so as to cause the colored light generating element to emit, during the off state, some amount of light greater than a minimum amount of light that the light generating element is capable of generating while part of an active system. In some implementations, two or more offset voltages or currents can be applied. Implementations may include a preprocessor configured to receive an image signal and optimize color saturation of the image signal, such as by limiting and non-linearly increasing color saturation. Implementations may include multiple colored light generating elements.
摘要:
A graphics controller for a System-On-a-Chip (SOC) used with a battery-powered device allows for reduced-power display modes. The microprocessor writes to a frame buffer that is a single, contiguous address block in virtual memory. A memory management unit (MMU) translates frame-buffer address to multiple physical blocks. The graphics controller fetches pixels from the multiple physical blocks, including a block in an on-chip memory and a block in an external memory. In a low-power mode, pixels are only fetched from the lower-power on-chip memory and not the higher-power external memory. A smaller display window is defined and pixels outside the window are replaced by dummy data, .eliminating external-memory fetches. The smaller display window falls within the first block in the on-chip memory. Status and other information can be displayed in the smaller display window during stand-by modes, while a full-screen of data is displayed for full-power modes.
摘要:
A colored light generating element can be configured to, while in an active state, pulse between an off state and an on state. A substantially constant offset voltage or current can be applied to the colored light generating element during a predetermined time interval when the light generating element is in the off state so as to cause the colored light generating element to emit, during the off state, some amount of light greater than a minimum amount of light that the light generating element is capable of generating while part of an active system. In some implementations, two or more offset voltages or currents can be applied. Implementations may include a preprocessor configured to receive an image signal and optimize color saturation of the image signal, such as by limiting and non-linearly increasing color saturation. Implementations may include multiple colored light generating elements.
摘要:
A method and system for cross color elimination is disclosed in processing of a component video signal comprising component luminance and chrominance information. Aspects of the exemplary embodiments include using separated luminance and chrominance information for each pixel in a current frame, getting absolute distance values between C=a current frame pixel color, P=a previous frame pixel color, H=a high frequency color of the previous frame, and O=a center of a color space; comparing each absolute distance value with a predetermined threshold, wherein if any of the absolute distance values exceed the predetermined threshold, then the pixel is a cross color pixel; and for each cross color pixel, replacing a current frame pixel color with a high frequency average pixel color.
摘要:
A dynamic random access memory (DRAM) circuit operates in burst mode when a row address strobe (RAS) signal is applied while an output enable/burst enable signal is also applied thereto. During burst mode, a column address strobe (CAS) signal is toggled to access digital data from sequential column addresses within a given row.
摘要:
A memory device utilized for an image display apparatus, such as a dual port memory. The memory device provides a serial port for performing a serial-access with a display controller and a random port for performing a random-access with a CPU. Such memory device includes memory cell arrays of M rows and N columns, one couple of data registers and pointers. The data stored in one row within the memory cell arrays are divided into data of K columns and another data of N-K columns. When the display controller performs the serial-access, one of the above two data registers can be alternatively used for serially inputting or outputting the data while the another data are transferred between the memory cell arrays and another data register. Or the data can be transferred between the memory cell arrays and both of two data registers. In this case, the serial input or output positions for determining the start addresses are assigned by the pointers. The data are read from or written into the data registers from the start addresses.
摘要:
A video RAM write control circuit has a video RAM for storing pattern data of one frame at addresses thereof which correspond to display positions, and a control circuit for generating write pattern data and write addresses. The video RAM stores a pattern which is continuous in the horizontal direction, at consecutive addresses thereof. Each row on the screen consists of several rasters. A video RAM address has a memory address representing a position in the horizontal direction, in its lower bits, so well as a raster address representing a raster position of the row, at upper bits thereof. A write address is rotated toward the MSB by the number of bits of the raster address, and a resultant permuted address is supplied to the video RAM.
摘要:
An image display apparatus reads color data and attribute data accompanied with the color data from a RAM of a look-up table (LUT) in accordance with each color code read from a video memory (VRAM). The read color data is subjected to a data modification determined by the read attribute data, and a color of each display dot is determined in accordance with the color data obtained as the result of the data modification. According to this image display apparatus, an image and the color thereof can be displayed without storing all the color codes of the image into the VRAM, so that the load on the CPU can be reduced and the image can be displayed at a high speed. The LUT can be omitted by storing, correspondingly to each display dot, display data composed of color data and attribute data in the VRAM. The circuit for effecting the data modification may comprise a plurality of registers and an operation circuit for effecting an operation on data contained in the registers. In this case, the registers and the operation circuit are controlled in accordance with the read attribute data to obtain various display effects such as Gouraud Shading and Phong Shading.
摘要:
A display controller displays an image on either of a CRT display unit and a liquid crystal display unit (LCD) having upper and lower screens in accordance with image data stored in a memory. When a CRT display unit is driven, an address generating circuit calculates at the beginning of each horizontal scanning an address of the memory corresponding to the leftmost display position on the current horizontal scanning line in accordance with the vertical position of the horizontal scanning line and the number of display positions on a horizontal scanning line, and stores data representing the address in a first register. The data in the first register is incremented in accordance with the horizontal scanning and fed to the memory to read the image data. When the LCD is driven, the address generating circuit calculates at the beginning of each horizontal scanning two addresses of the memory corresponding respectively to the left most display positions on the current horizontal scanning lines on the upper and lower screens. In this case, the first one is obtained in accordance with the vertical position of the current horizontal scanning line on the upper screen and the number of display positions on a horizontal scanning line, while the second one is obtained by adding the number of display positions on the upper screen to the calculated first address.