公开(公告)号：US5136543A

公开(公告)日：1992-08-04

申请号：US741208

申请日：1991-07-31

申请人： Yoshio Matsuda ,  Kazuyasu Fujishima ,  Kazutami Arimoto ,  Masaki Tsukude ,  Tsukasa Oishi

发明人： Yoshio Matsuda ,  Kazuyasu Fujishima ,  Kazutami Arimoto ,  Masaki Tsukude ,  Tsukasa Oishi

IPC分类号： G11C7/10

CPC分类号： G11C7/1006

摘要： A semiconductor memory device comprises a plurality of bit line pairs and an input/output line pair. Each bit line pair comprises first and second bit lines supplied with complementary data, and the input/output line pair comprises first and second input/output lines supplied with complementary data. A switching circuit is provided on each bit line pair. Each switching circuit, in response to a control signal according to an address signal, respectively couples the first and the second bit lines to the first and the second input/output lines, or inversely, respectively couples the first and the second bit lines to the second and the first input/output lines.

摘要翻译： 半导体存储器件包括多个位线对和一个输入/输出线对。 每个位线对包括提供有互补数据的第一和第二位线，并且输入/输出线对包括提供有互补数据的第一和第二输入/输出线。 在每个位线对上提供开关电路。 每个开关电路响应于根据地址信号的控制信号分别将第一和第二位线耦合到第一和第二输入/输出线，或者相反地将第一和第二位线耦合到 第二个和第一个输入/输出线。

公开(公告)号：US4811304A

公开(公告)日：1989-03-07

申请号：US838303

申请日：1986-03-10

申请人： Yoshio Matsuda ,  Hideshi Miyatake ,  Kazuyasu Fujishima

发明人： Yoshio Matsuda ,  Hideshi Miyatake ,  Kazuyasu Fujishima

IPC分类号： G11C11/407 ,  G11C8/08 ,  G11C8/10 ,  H01L27/04 ,  H01L27/108 ,  G11C8/00 ,  H03K19/094 ,  H03K19/20

CPC分类号： G11C8/10 ,  G11C8/08

摘要： A dynamic random access memory device having common signal lines to transmit row address signals and column address signals, uses change-over switches to transfer those signals to a row decoder. Voltage suppression circuitry limits high voltage applied to decoupling transistors provided at decoder outputs. An MOS transistor used as a voltage suppression device between the decoupling transistor and a word line activating transistor transfers word line activating signals.

摘要翻译： 具有用于发送行地址信号和列地址信号的公共信号线的动态随机存取存储器件使用转换开关将这些信号传送到行解码器。 电压抑制电路限制了施加到解码器输出端提供的去耦晶体管的高电压。 用作去耦晶体管和字线激活晶体管之间的电压抑制器件的MOS晶体管传输字线激活信号。

公开(公告)号：US5289417A

公开(公告)日：1994-02-22

申请号：US958466

申请日：1992-10-08

申请人： Tsukasa Ooishi ,  Yoshio Matsuda ,  Kazutami Arimoto ,  Masaki Tsukude ,  Kazuyasu Fujishima

发明人： Tsukasa Ooishi ,  Yoshio Matsuda ,  Kazutami Arimoto ,  Masaki Tsukude ,  Kazuyasu Fujishima

IPC分类号： G11C29/00

CPC分类号： G11C29/806 ,  G11C29/781

摘要： A semiconductor memory device comprises two memory cell arrays (1a, 1b) in which a block divisional operation is performed. Two spare rows (2a, 2b) are provided corresponding to the two memory cell arrays (1a, 1b). Spare row decoders (5a, 5b) are provided for selecting the spare rows (2a, 2b), respectively. One spare row decoder selecting signal generation circuit (18) used in common by the spare row decoders (5a, 5b) is provided. The spare row decoder selecting signal generation circuit (18) can be previously set so as to generate a spare row decoder selecting signal (SRE) when a defective row exists in either of the memory cell arrays (1a, 1b) and the defective row is selected by row decoder groups (4a, 4b). Each of the spare row decoders (5a, 5b) is activated in response to the spare row decoder selecting signal (SRE) and a block control signal.

摘要翻译： 半导体存储器件包括执行块分割操作的两个存储单元阵列（1a，1b）。 对应于两个存储单元阵列（1a，1b）提供两个备用行（2a，2b）。 备用排解码器​​（5a，5b）分别用于选择备用行（2a，2b）。 提供了由备用行解码器（5a，5b）共同使用的一个备用行解码器选择信号生成电路（18）。 可以预先设置备用行解码器选择信号生成电路（18），以便当在存储单元阵列（1a，1b）中存在有缺陷行时产生备用行译码器选择信号（S（OVS）），并且 有缺陷的行由行解码器组（4a，4b）选择。 每个备用行解码器（5a，5b）响应于备用行解码器选择信号（S（OVS））和块控制信号被激活。

公开(公告)号：US5185744A

公开(公告)日：1993-02-09

申请号：US479568

申请日：1990-02-14

申请人： Kazutami Arimoto ,  Kazuyasu Fujishima ,  Yoshio Matsuda ,  Tsukasa Ooishi ,  Masaki Tsukude

发明人： Kazutami Arimoto ,  Kazuyasu Fujishima ,  Yoshio Matsuda ,  Tsukasa Ooishi ,  Masaki Tsukude

IPC分类号： G11C29/00 ,  G11C11/401 ,  G11C29/28 ,  G11C29/34 ,  G11C29/40

CPC分类号： G11C29/40 ,  G11C29/28

摘要： A semiconductor memory device comprises a plurality of memory array blocks (B1 to B4). In each of the plurality of memory array blocks (B1 to B4), a line mode test is performed. Results of the line mode tests performed in the memory array blocks (B1 to B4) are outputted to corresponding match lines (ML1 to ML4). A flag compress (30) performs a logic operation on the test results outputted to the plurality of match lines (ML1 to ML4) and outputs the operation results as test results for the plurality of memory array blocks (B1 to B4) to the outside.

摘要翻译： 半导体存储器件包括多个存储器阵列块（B1至B4）。 在多个存储器阵列块（B1〜B4）的每一个中，进行线路模式测试。 在存储器阵列块（B1〜B4）中执行的线路模式测试的结果被输出到对应的匹配线（ML1〜ML4）。 标志压缩（30）对输出到多个匹配线（ML1〜ML4）的测试结果进行逻辑运算，并将作为多个存储器阵列块（B1〜B4）的测试结果的运算结果输出到外部。

公开(公告)号：US5184327A

公开(公告)日：1993-02-02

申请号：US727218

申请日：1991-07-09

申请人： Yoshio Matsuda ,  Kazutami Arimoto ,  Tsukasa Ooishi ,  Masaki Tsukude ,  Kazuyasu Fujishima

发明人： Yoshio Matsuda ,  Kazutami Arimoto ,  Tsukasa Ooishi ,  Masaki Tsukude ,  Kazuyasu Fujishima

IPC分类号： G11C29/30

CPC分类号： G11C29/30

摘要： In a memory cell array of a semiconductor memory device, a plurality of detection circuits (14, 15, 20) are provided in correspondence with a plurality of columns. An output line (L) is provided in common to the detection circuits (14, 15 20). The output line (L) is provided with plural junction points (n1 to nn) to which detection results from the detection circuits (14, 15 20) are separately applied. Dividing transistors (T1 to Tn) are provided between the junction points (n1 to nn). During testing, the word lines (WL1 to WLn) are selected sequentially. Test results for the memory cells (MC1 to MC4) connected to the selected word line are outputted at the corresponding junction points (n1 to nn), respectively. Simultaneously, a dividing transistor corresponding to the selected word line is rendered non-conductive, the remaining dividing transistors being rendered conductive. As a result, the output line (L) is divided into two parts at a portion of the non-conductive transistor. Detection results outputted to the respective divided parts of the output line (L) are monitored and a portion at which a detection result is changed in each divided part is found out.

摘要翻译： 在半导体存储器件的存储单元阵列中，与多个列对应地提供多个检测电路（14,15,20）。 输出线（L）与检测电路（14,1520）共同设置。 输出线（L）具有分别施加有检测电路（14,15,20）的检测结果的多个连接点（n1〜nn）。 分接晶体管（T1至Tn）设置在连接点（n1至nn）之间。 在测试期间，顺序选择字线（WL1至WLn）。 连接到所选字线的存储单元（MC1至MC4）的测试结果分别在对应的连接点（n1至nn）输出。 同时，与所选字线对应的分割晶体管不导通，剩余的分割晶体管导通。 结果，输出线（L）在非导电晶体管的一部分被分成两部分。 检测输出到输出线（L）的分割部分的检测结果，并且求出检测结果在各分割部分发生变化的部分。

公开(公告)号：US5088063A

公开(公告)日：1992-02-11

申请号：US532338

申请日：1990-06-05

申请人： Yoshio Matsuda ,  Kazutami Arimoto ,  Tsukasa Ooishi ,  Masaki Tsukude ,  Kazuyasu Fujishima

发明人： Yoshio Matsuda ,  Kazutami Arimoto ,  Tsukasa Ooishi ,  Masaki Tsukude ,  Kazuyasu Fujishima

IPC分类号： G11C11/401 ,  G11C11/407 ,  G11C29/00 ,  G11C29/30 ,  G11C29/34

CPC分类号： G11C29/30

摘要： In a memory cell array of a semiconductor memory device, a plurality of detection circuits (14, 15, 20) are provided in correspondence with a plurality of columns. An output line (L) is provided in common to the detection circuits (14, 15, 20). The output line (L) is provided with plural junction points (nl to nn) to which detection results from the detection circuits (14, 15, 20) are separately applied. Dividing transistors (Tl to Tn) are provided between the junction points (nl to nn). During testing, the work lines (WLl to WLn) are selected sequentially. Test results for the memory cells (MC1 to MC4 ) connected to the selected word line are outputted at the corresponding junction points (nl to nn), respectively. Simultaneously, a dividing transistor corresponding to the selected word line is rendered non-conductive, the remaining dividing transistors being rendered conductive. As a result, the output line (L) is divided into two parts at a portion of the non-conductive transistor. Detection results outputted to the respective divided parts of the output line (L) are monitored and a portion at which a detection result is changed in each divided part is found out.

摘要翻译： 在半导体存储器件的存储单元阵列中，与多个列对应地提供多个检测电路（14,15,20）。 输出线（L）与检测电路（14,15,20）共同设置。 输出线（L）设置有分别施加有来自检测电路（14,15,20）的检测结果的多个结点（n1至nn）。 分接晶体管（T1至Tn）设置在连接点（nl至nn）之间。 在测试期间，依次选择工作线（WL1至WLn）。 连接到所选字线的存储单元（MC1至MC4）的测试结果分别在对应的连接点（nl至nn）输出。 同时，与所选字线对应的分割晶体管不导通，剩余的分割晶体管导通。 结果，输出线（L）在非导电晶体管的一部分被分成两部分。 检测输出到输出线（L）的分割部分的检测结果，并且求出检测结果在各分割部分发生变化的部分。

公开(公告)号：US5060230A

公开(公告)日：1991-10-22

申请号：US400899

申请日：1989-08-30

申请人： Kazutami Arimoto ,  Kazuyasu Fujishima ,  Yoshio Matsuda ,  Tsukasa Ooishi ,  Masaki Tsukude

发明人： Kazutami Arimoto ,  Kazuyasu Fujishima ,  Yoshio Matsuda ,  Tsukasa Ooishi ,  Masaki Tsukude

IPC分类号： G06F11/267 ,  G11C29/00 ,  G11C29/12 ,  G11C29/34

CPC分类号： G11C29/78 ,  G11C29/12 ,  G11C29/34 ,  G06F11/267

摘要： An apparatus for parallel testing of a semiconductor memory with arbitrary data patterns and capable of being integrated on the memory chip. The semiconductor memory test device in a preferred embodiment is compatible with hierarchical data bus lines including an input/output line pair (I/O, I/O), a plurality of sub-input/output line pairs (SIO1SIO1; SIO2, SIO2) and a plurality of bit line pairs (BL1, BL1; BL6, BL6). A plurality of comparators (50) and a plurality of registers (60) are provided corresponding to a plurality of sub-input/output line pairs (SIO1, SIO2; SIO2, SIO2). The plurality of registers (50) which also functions as intermediated output amplifiers can hold random data applied through the input/output line pair (I/O, I/O). The plurality of comparators (60) is provided to determine whether or not data read out onto a plurality of sub-input/output line pairs (SIO1, SIO1; SIO2, SIO2) from a row of memory cells (MC1, MC2) corresponding to a single word line (WL) match respective data held in the plurality of registers (60).

摘要翻译： 一种用于并行测试具有任意数据模式并能够集成在存储器芯片上的半导体存储器的装置。 优选实施例中的半导体存储器测试装置与包括输入/​​输出线对（I / O，I / O），多个子输入/输出线对（SIO1 + L，SIO1; SIO2，SIO2）和多个位线对（BL1，BL1; BL6，BL6）。 对应于多个子输入/输出线对（SIO1，SIO2; SIO2，SIO2）提供多个比较器（50）和多个寄存器（60）。 也可以用作中间输出放大器的多个寄存器（50）可以保存通过输入/输出线对（I / O，I / O）施加的随机数据。 多个比较器（60）被提供以确定从对应于存储单元（MC1，MC2）的一行的多个子输入/输出线对（SIO1，SIO1; SIO2，SIO2） 单个字线（WL）匹配保存在多个寄存器（60）中的相应数据。

公开(公告)号：US4980310A

公开(公告)日：1990-12-25

申请号：US412742

申请日：1989-09-26

申请人： Yoshio Matsuda ,  Kazuyasu Fujishima

发明人： Yoshio Matsuda ,  Kazuyasu Fujishima

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10829 ,  Y10S257/911

摘要： A dynamic semiconductor memory device comprising a substrate having one trench including two capacitors for memory cell capacitances of two bits, and two elements such as transistors for reading, writing, and storing information represented by charge, arranged symmetrically at the central portion of the trench so as to correspond to the memory cells for two bits, and a field oxide film formed at the center of the trench on the bottom and on the side walls for separating the capacitors and elements.

公开(公告)号：US4972380A

公开(公告)日：1990-11-20

申请号：US206416

申请日：1988-06-14

申请人： Hideto Hidaka ,  Kazuyasu Fujishima ,  Yoshio Matsuda

发明人： Hideto Hidaka ,  Kazuyasu Fujishima ,  Yoshio Matsuda

IPC分类号： H01L21/82 ,  G11C5/06 ,  G11C8/00 ,  G11C8/12 ,  G11C11/401 ,  G11C29/00 ,  H01L21/822 ,  H01L27/04 ,  H01L27/10 ,  H03M7/00 ,  H03M7/22

CPC分类号： G11C8/12 ,  G11C5/066 ,  G11C29/006

摘要： An address decoding circuit for a functional block comprises branch portions serially connected with each other, in which a selecting signal is outputted on one of two output portions in accordance with the first bit information of an address signal when a selecting signal is applied to the first stage branch portion. The second stage output portion, to which the selecting signal is applied, outputs a selecting signal on one of two output portions in response to the second bit information of the address signal, in accordance with the selecting signal. Thereafter, each branch portion of the third to last stages outputs a selecting signal on one of two output portions in response to respective contents of the third bit to last bit of the address signal in accordance with the selecting signal applied from the preceding stage. By this selecting signal, a memory cell as a functional block portion is selected and is activated.

摘要翻译： 用于功能块的地址解码电路包括彼此串行连接的分支部分，其中当选择信号被施加到第一个时，根据地址信号的第一位信息在两个输出部分之一上输出选择信号 阶段分支部分。 根据选择信号，施加选择信号的第二级输出部分响应于地址信号的第二位信息，在两个输出部分之一上输出选择信号。 此后，根据从前一级施加的选择信号，第三至最后级的每个分支部分响应于第三位的相应内容输出地址信号的最后一位的两个输出部分之一上的选择信号。 通过该选择信号，选择作为功能块部分的存储单元并被激活。

公开(公告)号：US4890261A

公开(公告)日：1989-12-26

申请号：US206417

申请日：1988-06-14

申请人： Hideto Hidaka ,  Kazuyasu Fujishima ,  Yoshio Matsuda

发明人： Hideto Hidaka ,  Kazuyasu Fujishima ,  Yoshio Matsuda

IPC分类号： G11C7/00 ,  G06F12/04 ,  G11C7/10 ,  G11C8/12 ,  G11C11/401

CPC分类号： G11C8/12 ,  G11C7/1006

摘要： A word length variable circuit of a semiconductor memory comprises a shift register provided corresponding to rows or columns of a memory cell array. The input of the first stage of the shift register is connected to the output of the last stage and regions of the shift register is grouped to form a fixed recirculation path. The word length can be varied by modifying stored data in the shift register without changing its recirculation path.

摘要翻译： 半导体存储器的字长可变电路包括与存储单元阵列的行或列对应地设置的移位寄存器。 移位寄存器的第一级的输入连接到最后级的输出端，移位寄存器的区域被分组以形成固定的再循环路径。 可以通过修改移位寄存器中存储的数据而不改变其再循环路径来改变字长。