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41.发明授权Digital equalizer capable of varying the center frequency, quality factor, and gain to perform various frequency characteristics 失效数字均衡器能够改变中心频率，品质因数和增益，以执行各种频率特性
公开(公告)号：US4524422A
公开(公告)日：1985-06-18
申请号：US187328
申请日：1980-09-15
申请人： Masao Kasuga
发明人： Masao Kasuga
摘要： A digital filter having a band-pass filter characteristic or a band-elimination characteristic is constructed by a designing procedure comprising a step in which a function H(z) is obtained from a Z-transform of a bi-quad transfer function H(s) in a Laplace transfer form comprising conjugate pairs of poles and zeros, and establishing a center frequency of the filter characteristic from the radius of a circle in the s-plane in which the poles and zeros of the bi-quad transfer function H(s) are on the same circle, a step in which a quality factor Q of the filter characteristic is established so as to satisfy the following two equations (I) and (II) in which .sigma..sub.1 is the real-axis projection part and .omega..sub.1 is the imaginary-axis projection part of the above two poles in the s-plane, and .sigma..sub.2 is the real-axis projection part and .omega..sub.2 is the imaginary-axis projection part of the above two zeros, and a step in which a gain at the center frequency of the filter characteristic is established from a ratio .sigma..sub.2 /.sigma..sub.1 of the real-axis projection part .sigma..sub.1 of the poles and the real-axis projection part .sigma..sub.2 of the zeros in the s-plane ##EQU1##
摘要翻译： 具有带通滤波器特性或带消除特性的数字滤波器通过包括以下步骤的设计过程构成，其中从双向传递函数H（s）的Z变换获得函数H（z） ），包括共轭极点和零点的拉普拉斯转移形式，并且从双平面传递函数H（s）的极点和零点的s平面中的圆的半径建立滤波器特征的中心频率 ）在同一个圆上，其中建立了滤波器特性的质量因子Q以满足以下两个等式（I）和（II）的步骤，其中σ1是实轴投影部分，ω1 是s平面中上述两极的虚轴投影部分，sigma2是实轴投影部分，ω2是上述两个零点的虚轴投影部分，其中a 在滤波器特性的中心频率处的增益是esta （s）中的零点的实轴投影部分σ1与实线轴投影部分sigma 2的比率sigma 2 / s 1发生，
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公开(公告)号：US4471381A
公开(公告)日：1984-09-11
申请号：US357132
申请日：1982-03-11
CPC分类号： H04N7/0135 , H04N7/01
摘要： A system for converting number of scanning lines converts a first number of scanning lines of a first digital video signal into a second number of scanning lines of a second digital video signal. The system comprises a discrete signal obtaining circuit supplied with the first digital video signal, for successively re-arranging a plurality of picture element information arranged along lines in a vertical direction with respect to a picture frame indicated by the first digital video signal within a time interval corresponding to the first number of scanning lines in units of each of the lines in the vertical direction in a time series manner, to obtain a discrete signal having a sampling frequency equal to a horizontal scanning frequency of the first digital video signal, a sampling frequency converter for converting the sampling frequency of the discrete signal obtained from the discrete signal obtaining circuit into a frequency equal to a horizontal scanning frequency of the second digital video signal, and a second video signal obtaining circuit for successively re-arranging an output of the sampling frequency converter in units of a plurality of picture element information along a direction of horizontal scanning lines in accordance with the second digital video signal in a time series manner, to obtain the second digital video signal using the second number of scanning lines.
摘要翻译： 用于转换扫描线数量的系统将第一数字视频信号的第一数量的扫描线转换成第二数字视频信号的第二数量的扫描线。 该系统包括提供有第一数字视频信号的离散信号获取电路，用于在一段时间内相对于由第一数字视频信号指示的画面沿着垂直方向的线排列重新排列的多个像素信息 以与时间序列方式的垂直方向上的每行的单位相对应的第一扫描线数的间隔，以获得具有等于第一数字视频信号的水平扫描频率的采样频率的离散信号，采样 频率转换器，用于将从离散信号获取电路获得的离散信号的采样频率转换成等于第二数字视频信号的水平扫描频率的频率;以及第二视频信号获取电路，用于连续重新布置 采样频率转换器以多个像素信息a1为单位 以时间序列方式按照第二数字视频信号的水平扫描线的方向，使用第二数量的扫描线来获得第二数字视频信号。
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公开(公告)号：US4472785A
公开(公告)日：1984-09-18
申请号：US311095
申请日：1981-10-13
申请人： Masao Kasuga
发明人： Masao Kasuga
CPC分类号： H03H17/0288 , H03H17/0685
摘要： A sampling frequency converter for converting a first signal sampled at a first sampling frequency f1 into a second signal sampled at a second sampling frequency f2 comprising an interpolation device supplied with the first signal, for inserting L-1 zeros (L is an integer) for every sampling time, a filter circuit for attenuating a frequency component over a frequency f/2 (f is a frequency) within an output signal of said interpolation device, where the filter circuit has a series circuit consisting of a finite impulse response digital filter and an infinite impulse response digital filter, and the frequency f is equal to the first sampling frequency f1 when f1 f2, and a decimation device for extracting every M-th (M is an integer) output signal of the filter circuit, to produce said second signal.
摘要翻译： 一种采样频率转换器，用于将以第一采样频率f1采样的第一信号转换为第二采样频率f2采样的第二信号，包括提供有第一信号的内插装置，用于插入L-1个零（L为整数），用于 每个采样时间，用于在所述内插装置的输出信号内对频率f / 2（f是频率）频率分量进行衰减的滤波器电路，其中滤波电路具有由有限脉冲响应数字滤波器和 无限脉冲响应数字滤波器，并且当f1
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公开(公告)号：US4453255A
公开(公告)日：1984-06-05
申请号：US345459
申请日：1982-02-03
申请人： Yoshiyuki Tsuchikane , Masao Kasuga
发明人： Yoshiyuki Tsuchikane , Masao Kasuga
CPC分类号： G11B5/035 , H03G5/005 , H03G5/025 , H04L25/03146
摘要： A characteristic control system for a digital equalizer comprises a digital equalizer constructed from a digital filter, for directly giving a desired equalizing characteristic with respect to a digital pulse-modulated signal, and a control part for changing the equalizing characteristic of the digital equalizer from a first arbitrary characteristic to a second arbitrary characteristic so that one or a plurality of intermediate equalizing characteristic is obtained before reaching the desired second arbitrary characteristic.
摘要翻译： 用于数字均衡器的特征控制系统包括由数字滤波器构成的数字均衡器，用于直接给出相对于数字脉冲调制信号的所需均衡特性，以及用于从数字均衡器改变数字均衡器的均衡特性的控制部分 第二任意特性的第一任意特征，使得在达到期望的第二任意特性之前获得一个或多个中间均衡特性。
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45.发明授权
公开(公告)号：US4366471A
公开(公告)日：1982-12-28
申请号：US236633
申请日：1981-02-20
申请人： Masao Kasuga
发明人： Masao Kasuga
CPC分类号： G11B27/005
摘要： A variable speed reproduction system includes a memory in which analog signal is stored as sampled digital data. A variable frequency digital low-pass filter is receptive of the data read out of the memory. A counter provides a binary representation of a count value of time base clock pulses to a comparator for detecting a coincidence with a variable speed setting of a variable resistor. The output of the comparator resets the counter and is used as a source of reading the data out of the memory. The cut-off frequency of the digital filter is controlled in response to the setting of the resistor so that the high frequency component of the analog equivalent of the input digital data which is higher than one-half of the data reading frequency is eliminated to prevent foldover distortion noise which might occur as a result of the difference between the recording and reproducing speeds. The data read out of the memory is fed to a digital-to-analog converter at a constant frequency and the quantum noise of the output data is filtered out by an analog low-pass filter.
摘要翻译： 变速再现系统包括存储模拟信号作为采样数字数据存储的存储器。 可变频数字低通滤波器可接收从存储器读出的数据。 计数器向比较器提供时基脉冲时钟脉冲的计数值的二进制表示，用于检测与可变电阻器的可变速度设置的一致。 比较器的输出复位计数器，并用作从存储器读出数据的源。 数字滤波器的截止频率响应于电阻器的设置而被控制，使得高于数据读取频率的一半的输入数字数据的模拟等效的高频分量被消除以防止 可能由于记录和再现速度之间的差异而发生的倒塌变形噪声。 从存储器读出的数据以恒定频率馈送到数模转换器，并且输出数据的量子噪声由模拟低通滤波器滤除。
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公开(公告)号：US4186281A
公开(公告)日：1980-01-29
申请号：US843863
申请日：1977-10-20
申请人： Masao Kasuga , Nobuaki Takahashi , Fujio Suzuki , Yoshiki Iwasaki
发明人： Masao Kasuga , Nobuaki Takahashi , Fujio Suzuki , Yoshiki Iwasaki
CPC分类号： H04S3/006
摘要： A multichannel record disc reproducing apparatus comprises a first phase locked loop circuit including a phase comparator and a voltage controlled oscillator for demodulating an angle-modulated wave signal. The modulated signal is separated from a composite signal picked up from a multichannel record disc on which a multiplexed direct wave signal and an angle-modulated wave signal are recorded. The output of the first phase locked loop is a demodulated signal. A second phase locked loop circuit includes a phase comparator and a voltage controlled oscillator, supplied with the separated angle-modulated wave signal and having a lock range of a width which covers and is wider than the maximum lock range width of the first phase locked loop circuit. A synchronous detector compares the phases of the angle-modulated wave signal and the output signal of voltage controlled oscillator of the second phase locked loop. The synchronous detector operates when the phase difference of the two signals deviates sufficiently from a predetermined phase difference. Means are provided for reducing or removing noise components which are developed in the demodulated signal in accordance with the output of the synchronous detector. This noise reduction or removal is provided in the first phase locked loop circuit and/or in a channel for transmitting the demodulated signal.
摘要翻译： 多通道记录盘重放装置包括第一锁相环电路，其包括用于解调角度调制波信号的相位比较器和压控振荡器。 调制信号与从其上记录有多路复用直接波信号和角度调制波信号的多通道记录盘拾取的复合信号分离。 第一锁相环的输出是解调信号。 第二锁相环电路包括相位比较器和压控振荡器，被提供有分离的角度调制波信号并且具有覆盖并且比第一锁相环的最大锁定范围宽度宽的宽度的锁定范围 电路。 同步检波器将角度调制波信号的相位与第二锁相环的压控振荡器的输出信号进行比较。 当两个信号的相位差从预定的相位差充分偏离时，同步检测器工作。 提供了用于根据同步检测器的输出减少或去除在解调信号中产生的噪声分量的装置。 在第一锁相环电路和/或用于发送解调信号的信道中提供该噪声降低或去除。
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公开(公告)号：US6064139A
公开(公告)日：2000-05-16
申请号：US321581
申请日：1994-10-11
申请人： Fujio Ozawa , Takashi Sato , Masao Kasuga , Shuji Otawa
发明人： Fujio Ozawa , Takashi Sato , Masao Kasuga , Shuji Otawa
摘要： An ultrasonic motor capable of being accurately step-driven comprises a vibrating member piezoelectrically vibrated for driving and halting a movable member. A driving wave is generated for vibrating the vibrating member to drive the movable member, and a halting wave is generated for vibrating the vibrating member to halt the movable member. The driving wave can be either a travelling wave or a standing wave, and the halting wave is a standing wave. The movable member is divided into a plurality of portions, and when the vibrating member is driven by the halting wave, the portions of the movable member become centered at respective nodal portions of the standing halting wave, causing the movable member to stop rotating so that the ultrasonic motor can be accurately step-driven.
摘要翻译： 能够精确地逐步驱动的超声波马达包括压电振动的振动部件，用于驱动和停止可动部件。 产生用于使振动部件振动以驱动可动部件的驱动波，产生使振动部件振动以停止可动部件的停止波。 驱动波可以是行波还是驻波，停波是驻波。 可移动部件被分成多个部分，并且当振动部件被停止波驱动时，可移动部件的部分在驻停的波浪的相应节点处居中，从而使可动部件停止旋转，从而 超声波电机可以精确地逐级驱动。
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公开(公告)号：US5440192A
公开(公告)日：1995-08-08
申请号：US232873
申请日：1994-04-25
申请人： Masao Kasuga
发明人： Masao Kasuga
CPC分类号： H02N2/166
摘要： A thin, small-diameter, and efficient ultrasonic motor using a component of flexible travelling waves comprises a base, a stator and a rotor. The stator has an elastic vibrating body and a ceramic piezoelectric vibrator provided on one side of the elastic vibrating body. A central portion of the stator is secured and freely supported by a central support shaft.
摘要翻译： 使用柔性行波的部件的薄的，小直径的和有效的超声波马达包括基座，定子和转子。 定子具有弹性振动体和设置在弹性振动体一侧的陶瓷压电振动器。 定子的中心部分由中心支撑轴固定并自由地支撑。
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公开(公告)号：US5365139A
公开(公告)日：1994-11-15
申请号：US36033
申请日：1993-03-23
申请人： Masao Kasuga , Tatsunori Inoue , Jun Hirotomi , Hiroshi Kitamura
发明人： Masao Kasuga , Tatsunori Inoue , Jun Hirotomi , Hiroshi Kitamura
摘要： An electronic apparatus which is equipped with an ultrasonic motor and which consumes only a small amount of electric power, is stable in performance, and is capable of accurately controlling the angular position is offered.A driving pulse storage circuit stores driving pulses corresponding to the environment of the components of the ultrasonic motor. A stopping pulse storage circuit stores stopping pulses corresponding to the environment of the components of the motor. An environment detection means detects the environment of the components. An output pulse-selecting circuit receives the output signal from a driving pulse-generating circuit and the output signal from a stopping pulse-generating circuit and produces output pulses corresponding to the output signal from a detection signal-generating circuit to a piezoelectric vibrator-driving circuit. The moving member and the output means are operated by ultrasonic vibration of the vibrating member.
摘要翻译： 配备有超声波马达并且仅消耗少量电力的电子设备性能稳定，并且能够精确地控制角位置。 驱动脉冲存储电路存储对应于超声波马达的部件的环境的驱动脉冲。 停止脉冲存储电路存储对应于电动机的部件的环境的停止脉冲。 环境检测装置检测部件的环境。 输出脉冲选择电路接收来自驱动脉冲发生电路的输出信号和来自停止脉冲发生电路的输出信号，并产生与从检测信号发生电路到压电振动器驱动的输出信号相对应的输出脉冲 电路。 移动构件和输出装置通过振动构件的超声波振动来操作。
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公开(公告)号：US4355304A
公开(公告)日：1982-10-19
申请号：US217949
申请日：1980-12-18
申请人： Masao Kasuga , Norio Hiyama , Yoshiyuki Tsuchikane
发明人： Masao Kasuga , Norio Hiyama , Yoshiyuki Tsuchikane
CPC分类号： H04B14/048 , H03G7/007
摘要： A compressing system for digital modulated signals comprises an analog-to-digital converter for obtaining a digital modulated signal by digitally modulating an analog signal; a first variable gain circuit provided at the output side of the analog-to-digital converter; and a first gain control circuit for equivalently performing level-compression of the analog conversion level of the input digital modulated signal of the first gain control circuit within a predetermined level range by use of a first control signal and the first variable gain circuit. The first gain control circuit comprises an expected signal generating circuit having an analog conversion level z.sub.n which satisfies the equation ##EQU1## (N is an arbitrary natural number, and a.sub.O through a.sub.N are zero or an arbitrary number) where y.sub.n designates the analog conversion level of a digital modulated signal or the differential signal of the digital modulated signal at a time nT obtained from either the input side or output side of said first variable gain circuit (T indicates the sampling period of the digital modulated signal) and a.sub.i designates the coefficient used for the weighting, a variable reference level generator which generates a reference level, and a comparator which supplies the first control signal as output by comparing the reference level thus generated with the analog conversion level z.sub.n of the above expected signal. The expanding system comprises a second variable gain circuit supplied with the digital modulated signal obtained and transmitted from the first gain control circuit, which varies the analog conversion level of the input digital modulated signal according to a second control signal; a second gain control circuit for equivalently performing level-expansion of the analog conversion level of the input digital modulated signal of the second gain control circuit by the same quantity as the above level-compression within a predetermined level range by use of the second variable gain circuit and performing an opposite operation as that performed by the first gain control circuit with respect to the digital modulated signal obtained from either the input side or the output side of the second variable gain circuit, and a digital-to-analog converter for converting the output digital modulated signal of the second variable gain circuit into an analog signal.
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