公开(公告)号：US06801645B1

公开(公告)日：2004-10-05

申请号：US09602762

申请日：2000-06-23

申请人： Michael J. Collins ,  Steven K. Rogers ,  Richard A. Mitchell

发明人： Michael J. Collins ,  Steven K. Rogers ,  Richard A. Mitchell

IPC分类号： G06K900

CPC分类号： G06K9/6293 ,  G06K9/4609 ,  G06K9/56 ,  G06K2209/05 ,  G06T7/0012 ,  G06T2207/30068

摘要： A computer aided detection method and system to assist radiologists in the reading of medical images. The method and system has particular application to the area of mammography including detection of clustered microcalcifications and densities. A microcalcification detector is provided wherein individual detections are rank ordered and classified, and one of the features for classification is derived using a multilayer perceptron. A density detector is provided including an iterative, dynamic region growing module with embedded subsystem for rank ordering and classification of a best subset of candidate masks. A post processing stage is provided where detections are analyzed in the context of a set of images for a patient. Three analysis methods are used to distribute a limited number of detections across the image set and further within each image, and additionally to perform a normalcy classification. The normalcy classification is used to remove all detections from an image set when predetermined normalcy conditions are met. The final output of the system is a set of indications overlaid on the input medical images.

摘要翻译： 一种计算机辅助检测方法和系统，用于帮助放射科医师阅读医学图像。 该方法和系统在乳腺摄影领域具有特殊应用，包括检测聚类微钙化和密度。 提供了一种微钙化检测器，其中单独的检测是排序和分类的，并且使用多层感知器导出用于分类的特征之一。 提供了一种密度检测器，其包括具有嵌入式子系统的迭代动态区域增长模块，用于对候选掩模的最佳子集进行排序和分类。 提供后处理阶段，其中在用于患者的一组图像的上下文中分析检测。 三种分析方法用于跨越图像集并且进一步在每个图像内分布有限数量的检测，并且另外执行正常分类。 当满足预定的正常条件时，正常分类用于从图像集中去除所有检测。 系统的最终输出是覆盖在输入医学图像上的一组指示。

公开(公告)号：US06249847B1

公开(公告)日：2001-06-19

申请号：US09134057

申请日：1998-08-14

申请人： Kenneth T. Chin ,  Phillip M. Jones ,  Robert A. Lester ,  Gary J. Piccirillo ,  Michael J. Collins

发明人： Kenneth T. Chin ,  Phillip M. Jones ,  Robert A. Lester ,  Gary J. Piccirillo ,  Michael J. Collins

IPC分类号： G06F1378

CPC分类号： G06F13/18

摘要： A computer system that includes a CPU, a memory and a memory controller for controlling access to the memory. The memory controller generally includes arbitration logic for deciding which memory request among one or more pending requests should win arbitration. When a request wins arbitration, the arbitration logic asserts a “won” signal corresponding to that memory request. The memory controller also includes synchronizing logic to synchronize memory requests, corresponding to a first group of requests, that win arbitration to a clock signal and an arbitration enable signal. The synchronizing logic includes an AND gate and a latch for synchronizing the won signals. The memory controller also asynchronously arbitrates a second group of memory requests by asserting a won signal associated with the second group requests that is not synchronized to the clock signal. In this manner, the won signals for the second group of requests can be asserted earlier than the synchronized won signals, thereby permitting the asynchronously arbitrated second group memory requests to be performed earlier than otherwise possible.

摘要翻译： 一种包括CPU，存储器和用于控制对存储器的访问的存储器控​​制器的计算机系统。 存储器控制器通常包括仲裁逻辑，用于决定一个或多个待处理请求中哪个存储器请求应该赢得仲裁。 当请求赢得仲裁时，仲裁逻辑确定与该存储器请求对应的“赢”信号。 存储器控制器还包括同步逻辑，以将与第一组请求相对应的存储器请求同步到仲裁到时钟信号和仲裁使能信号。 同步逻辑包括与门和用于使获胜信号同步的锁存器。 存储器控制器还通过断言与不与时钟信号同步的第二组请求相关联的获胜信号来异步地仲裁第二组存储器请求。 以这种方式，第二组请求的获胜信号可以早于同步的获胜信号被断言，从而允许异步仲裁的第二组存储器请求比其他可能的更早执行。

公开(公告)号：US06175104B1

公开(公告)日：2001-01-16

申请号：US09148080

申请日：1998-09-04

申请人： Gary Roger Greene ,  Lois B. Jassie ,  Edward Earl King ,  Michael J. Collins

发明人： Gary Roger Greene ,  Lois B. Jassie ,  Edward Earl King ,  Michael J. Collins

IPC分类号： H05B664

CPC分类号： H05B6/806 ,  H05B6/70 ,  H05B6/72

摘要： A microwave heating system is disclosed for enhancing physical and chemical processes. The system includes a microwave source, an antenna having a cable, a receiver for receiving microwaves generated by the source, with the receiver being connected to a first end of the cable, and a transmitter for transmitting microwaves generated by the source, and with the transmitter being connected to an opposite end of the cable. The system also includes a reaction vessel with the transmitter inside the reaction vessel; and a microwave shield surrounding the transmitter for preventing microwaves emitted from the transmitter from extending substantially beyond the reaction vessel.

摘要翻译： 公开了用于增强物理和化学过程的微波加热系统。 该系统包括微波源，具有电缆的天线，用于接收由源产生的微波的接收器，接收器连接到电缆的第一端;以及发射器，用于传输源产生的微波，并且与 发射器连接到电缆的相对端。 该系统还包括在反应容器内具有变送器的反应容器; 以及围绕发射器的微波屏蔽，用于防止从发射器发射的微波基本上延伸超过反应容器。

公开(公告)号：US5848428A

公开(公告)日：1998-12-08

申请号：US770763

申请日：1996-12-19

申请人： Michael J. Collins

发明人： Michael J. Collins

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0864 ,  G06F2212/1028 ,  Y02B60/1225

摘要： A multiple-way cache memory system incorporating circuitry for selectively enabling the sense amplifiers in a given memory bank only when the memory bank contains data that is being accessed. In the disclosed embodiment of the invention, each bank of memory incorporates a bank of at least one sense amplifier that is enabled by a separate sense amplifier control signal. The sense amplifiers in each memory bank are controlled independent of the address decoding logic. Instead, the sense amplifier control signal for each memory bank is generated from tag RAM read hit information and read address data. Preferably, no more than one bank of sense amplifiers is enabled at a time, Power consumption in the cache memory system is thereby greatly reduced.

摘要翻译： 一种多路高速缓冲存储器系统，其结合电路，用于仅当存储体包含正被访问的数据时，才能选择性地使能给定存储体中的读出放大器。 在所公开的本发明的实施例中，每一组存储器都包含一个由一个单独的读出放大器控制信号使能的至少一个读出放大器组。 每个存储体中的读出放大器独立于地址解码逻辑进行控制。 而是从标签RAM读取命中信息和读取地址数据生成每个存储体的读出放大器控制信号。 优选地，一次启用不超过一组读出放大器，从而大大减少了高速缓冲存储器系统中的功耗。

公开(公告)号：US5809549A

公开(公告)日：1998-09-15

申请号：US801738

申请日：1997-02-14

申请人： Gary W. Thome ,  Michael J. Collins

发明人： Gary W. Thome ,  Michael J. Collins

IPC分类号： G06F13/42 ,  G11C7/10 ,  G11C7/22 ,  G11C8/18 ,  G06F13/28

CPC分类号： G11C8/18 ,  G06F13/4243 ,  G11C7/1018 ,  G11C7/22

摘要： Burst SRAMs designed for operation at a given data rate corresponding to the frequency of a first clock signal but capable of operation using a higher frequency clock signal. The burst SRAMs are preferably incorporated into the cache memory of a second level cache coupled to the processor bus in a computer system, where the computer system is preferably based on a 66-MHz P5 microprocessor. A cache controller, preferably incorporated within a memory controller, controls operation of the second level cache memory by providing the address load and address advance signals. The burst SRAMs are capable of recognizing the faster clock pulses, as well as the shorter pulses asserted on the address load and address advance signals. The address control signals are asserted and then negated during consecutive clock cycles of the faster clock signal, so that the burst SRAMs effectively operate at the same data rate corresponding to the lower frequency clock signal.

摘要翻译： 突发SRAM被设计为以对应于第一时钟信号的频率但能够使用较高频率时钟信号操作的给定数据速率进行操作。 突发SRAM优选地并入计算机系统中耦合到处理器总线的第二级高速缓冲存储器中，其中计算机系统优选地基于66MHz P5微处理器。 优选地并入存储器控制器内的高速缓存控制器通过提供地址负载和地址提前信号来控制第二级高速缓冲存储器的操作。 突发SRAM能够识别更快的时钟脉冲，以及在地址负载和地址提前信号上断言的较短脉冲。 在更快的时钟信号的连续时钟周期期间，地址控制信号被断言然后被否定，使得脉冲串SRAM以与较低频率时钟信号对应的相同数据速率有效地工作。

公开(公告)号：US5581727A

公开(公告)日：1996-12-03

申请号：US44379

申请日：1993-03-22

申请人： Michael J. Collins ,  Gary W. Thome

发明人： Michael J. Collins ,  Gary W. Thome

IPC分类号： G06F12/08

CPC分类号： G06F12/0804 ,  G06F12/0897

摘要： An apparatus for monitoring and decoding processor bus cycles and flushing a second level cache upon decoding a special flush acknowledge cycle. The CPU preferably includes an internal cache and a flush input for receiving a signal commanding the CPU to flush its internal cache. After flushing its cache by performing any necessary cycles to write back dirty data to main memory, the CPU performs a special flush acknowledge cycle to inform external devices that the flush procedure has been completed. A cache controller detects the flush acknowledge cycle and provides a flush signal to the second level cache. The cache controller then provides an end of cycle signal to the CPU to indicate that the flush cycle has been acknowledged.

公开(公告)号：US5403571A

公开(公告)日：1995-04-04

申请号：US700149

申请日：1991-04-04

申请人： Michael E Chalkley ,  Michael J. Collins ,  Manher M. Makwana ,  Ian M. Masters

发明人： Michael E Chalkley ,  Michael J. Collins ,  Manher M. Makwana ,  Ian M. Masters

IPC分类号： C01B17/02 ,  C01G13/00

CPC分类号： C01B17/0232 ,  C01G13/00

摘要： A process for removing mercury or other metal impurities from elemental sulphur contaminated therewith includes mixing such elemental sulphur in a molten state with an aqueous sulphide solution or an aqueous solution of sufficiently high pH which reacts with elemental sulphur and forms a sulphide solution to cause extraction of mercury or other metal contaminants from the elemental sulphur into the aqueous sulphide solutions, and separating the aqueous sulphide solution containing mercury or other metal contaminants from the molten elemental sulphur to provide an elemental sulphur product substantially free from mercury and other metal contaminants.

摘要翻译： PCT No.PCT / CA90 / 00187 Sec。 371日期：1991年4月9日 102（e）日期1991年4月9日PCT Filed 1990年6月5日PCT公布。 WO90 / 15021 PCT出版物 日期1990年12月13日。一种从被污染的元素硫中除去汞或其他金属杂质的方法包括将熔融状态的这种元素硫与硫化氢水溶液或足够高pH的水溶液混合，其与元素硫反应并形成 一种硫化物溶液，用于将汞或其他金属污染物从元素硫提取到硫化氢水溶液中，以及将含有汞或其它金属污染物的硫化氢水溶液与熔融元素硫分离，以提供基本上不含汞的元素硫产物， 其他金属污染物。

公开(公告)号：US5318754A

公开(公告)日：1994-06-07

申请号：US5252

申请日：1993-01-15

申请人： Michael J. Collins ,  Wyatt P. Hargett

发明人： Michael J. Collins ,  Wyatt P. Hargett

IPC分类号： B01J19/12 ,  B01L7/00 ,  C03B5/08 ,  C03B37/15 ,  F27D1/00 ,  F27D5/00 ,  F27D99/00 ,  G01N1/44 ,  G01N31/12 ,  G01N33/04 ,  H05B6/64 ,  H05B6/68 ,  H05B6/80

CPC分类号： H05B6/6455 ,  B01J19/126 ,  B01L7/00 ,  C03B37/15 ,  C03B5/08 ,  F27D5/0068 ,  G01N1/44 ,  G01N31/12 ,  H05B6/64 ,  H05B6/66 ,  B01J2219/1218 ,  F27D1/0009 ,  F27D2099/0028 ,  F27M2003/11 ,  G01N33/04

摘要： An apparatus for use in analyzing materials for ash content includes a walled chamber which retains microwave radiation therein, a source of microwave radiation, such as a magnetron, for radiating onto contents of such chamber, and an ashing furnace in the chamber which includes a heat resistant wall of low thermal conductivity, which is transmissive of microwave radiation, and a microwave absorptive material which is capable of being heated by microwave radiation to an ashing temperature. The furnace includes a passageway through it for the entry into the furnace cavity of a gas, such as air, and for venting gas, such as combustion products, from the furnace cavity, and preferably also includes a removable trapezoidally shaped door in a front wall thereof, which, when the chamber door is open, is readily removable from the furnace by hand, without burning the operator's fingers, despite the high internal temperature in the furnace cavity. Air flows through the chamber and around the furnace, helping to cool the exterior, of the furnace walls. It is preferred that the operation of the furnace and the ashing temperature be controlled by a combination of a temperature sensor, preferably a thermocouple, and a control mechanism, which turns the magnetron on and off as the temperature in the furnace cavity falls below or rises above a desired set temperature, respectively.

摘要翻译： 用于分析灰分材料的装置包括：保留微波辐射的壁室，诸如磁控管的微波辐射源，用于辐射到这种室的内容物上，以及在室中的灰化炉，其包括热量 微波辐射传播的低导热性的耐热壁，以及能够通过微波辐射加热至灰化温度的微波吸收材料。 炉子包括通过它的通道，用于进入诸如空气的气体的炉腔中，并且用于从炉腔排出诸如燃烧产物的气体，并且优选地还包括在前壁中的可移除的梯形门 其中，当室门打开时，即使在炉腔中具有高的内部温度，也可以用手轻轻地从炉子中移除炉子，而不燃烧操作者的手指。 空气流过室和炉周围，有助于冷却炉壁的外部。 优选的是，通过温度传感器，优选热电偶和控制机构的组合来控制炉的操作和灰化温度，控制机构随着炉腔中的温度降低或升高而使磁控管打开和关闭 分别高于所需的设定温度。

公开(公告)号：US5210850A

公开(公告)日：1993-05-11

申请号：US538724

申请日：1990-06-15

申请人： Philip C. Kelly ,  Michael J. Collins

发明人： Philip C. Kelly ,  Michael J. Collins

IPC分类号： G06F12/06 ,  G06F12/08

CPC分类号： G06F12/0888

摘要： An apparatus for determining cacheable address and write-protect memory address regions in a computer system which includes a programmable single-ended limit register and a single comparator to determine each such region. A programmable limit register associated with each respective memory address region defines a boundary limit for each of the respective memory regions. A single address comparator associated with each respective limit register determines whether a memory address developed by the computer system resides between the respective boundaries provided by the value stored in the respective programmable limit register and a predefined address. The use of a single limit register and a single address comparator for each memory address region reduces the gate count and decreases the input buffer loading in the logic circuitry.

公开(公告)号：US4763353A

公开(公告)日：1988-08-09

申请号：US830058

申请日：1986-02-14

申请人： Leonard M. Canale ,  Michael J. Collins ,  Paul J. O'Brien ,  Lisa L. Scott ,  Martin H. Singer

发明人： Leonard M. Canale ,  Michael J. Collins ,  Paul J. O'Brien ,  Lisa L. Scott ,  Martin H. Singer

IPC分类号： H04Q3/545 ,  H04M3/51 ,  H04M3/523 ,  H04Q3/58 ,  H04M3/50

CPC分类号： H04M3/5166 ,  H04M3/523

摘要： An adjunct call manager unit connects to a station set port of a telephone communication system and receives button identification and status signals to determine line, agent, and feature activation status of the system. In response to one or more of the received status signals, commands are sent to the system using button depression commands and switchhook commands to effectuate call processing control over the system. In one embodiment, the adjunct unit functions as an automated call distributor for managing incoming calls to the system.

摘要翻译： 附加呼叫管理器单元连接到电话通信系统的站设置端口，并接收按钮识别和状态信号，以确定系统的线路，代理和功能激活状态。 响应于接收到的一个或多个状态信号，使用按钮按钮命令和切换指令将命令发送到系统以实现对系统的呼叫处理控制。 在一个实施例中，辅助单元用作用于管理到系统的传入呼叫的​​自动呼叫分配器。