中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

60 records (took 0.017 seconds)

    Dedicated Memory Structure for Sector Spreading Interleaving
    43.
    发明申请
    Dedicated Memory Structure for Sector Spreading Interleaving 审中-公开
    用于扇区传播的专用存储器结构

    公开(公告)号：US20140244926A1

    公开(公告)日：2014-08-28

    申请号：US13777825

    申请日：2013-02-26

    Applicant: LSI CORPORATION

    Inventor： Shaohua Yang ,  Shu Li ,  Bruce A. Wilson

    IPC: G06F12/06

    CPC classification number: G11B5/012 ,  G11B20/10527 ,  G11B20/1217 ,  G11B20/1866

    Abstract: The present disclosure is directed to a method for managing a memory. The method includes the step of receiving data, the data including a plurality of sectors. The method also includes the step of dividing each sector of the plurality of sectors into a plurality of data units. A further step of the method involves interleaving the plurality of data units to yield a plurality of interleaved data units. The method also includes the step of writing the plurality of interleaved data units to a disk. An additional step of the method is to de-spread the plurality of interleaved data units to yield at least one sector of the plurality of sectors.

    Abstract translation: 本公开涉及一种用于管理存储器的方法。 该方法包括接收数据的步骤，该数据包括多个扇区。 该方法还包括将多个扇区中的每个扇区划分为多个数据单元的步骤。 该方法的另一步骤涉及交织多个数据单元以产生多个交错数据单元。 该方法还包括将多个交错数据单元写入盘的步骤。 该方法的附加步骤是解扩展多个交错数据单元以产生多个扇区中的至少一个扇区。

    Systems and methods for enhanced data encoding and decoding
    46.
    发明授权
    Systems and methods for enhanced data encoding and decoding 有权
    用于增强数据编码和解码的系统和方法

    公开(公告)号：US09196299B2

    公开(公告)日：2015-11-24

    申请号：US14025104

    申请日：2013-09-12

    Applicant: LSI Corporation

    Inventor： Bruce A. Wilson ,  Shaohua Yang ,  Shu Li

    IPC: G06F11/10 ,  G11B20/18 ,  H03M13/00

    CPC classification number: G11B20/1833 ,  G06F11/1076 ,  G11B2020/1853 ,  H03M13/00 ,  H03M13/1102 ,  H03M13/2909 ,  H03M13/293 ,  H03M13/41 ,  H03M13/6325 ,  H03M13/6343

    Abstract: Systems and methods relating generally to data processing, and more particularly to systems and methods for encoding and decoding information. As an example, a method is discussed that includes: applying a first level encoding on a section by section basis to a first data portion to yield a first encoding data including a first encoded portion; applying a second level encoding on a section by section basis to the first encoded portion to yield a first parity set; applying a third level encoding on a section by section basis to a combination of the first data portion, the second data portion, and a portion derived from the first encoded portion to yield a second encoding data.

    Abstract translation: 一般涉及数据处理的系统和方法，更具体地涉及用于编码和解码信息的系统和方法。 作为示例，讨论了一种方法，其包括：将逐级编码应用于第一数据部分，以产生包括第一编码部分的第一编码数据; 对第一编码部分逐个应用第二级编码以产生第一奇偶校验集; 对于第一数据部分，第二数据部分和从第一编码部分导出的部分的组合，逐个应用第三级编码，以产生第二编码数据。

    Low density parity check decoder with dynamic scaling
    49.
    发明授权
    Low density parity check decoder with dynamic scaling 有权
    低密度奇偶校验解码器，动态缩放

    公开(公告)号：US09130589B2

    公开(公告)日：2015-09-08

    申请号：US13777841

    申请日：2013-02-26

    Applicant: LSI Corporation

    Inventor： Shu Li ,  Zongwang Li ,  Shaohua Yang ,  Chung-Li Wang ,  Fan Zhang

    IPC: G11B20/18 ,  H03M13/13 ,  H03M13/11 ,  H03M13/00 ,  H03M13/27

    CPC classification number: H03M13/1117 ,  G11B20/1833 ,  G11B2020/185 ,  H03M13/1111 ,  H03M13/1171 ,  H03M13/27 ,  H03M13/6331 ,  H03M13/658

    Abstract: A data processing system is disclosed including a low density parity check decoder with a variable node processor, a check node processor and a scaler circuit. The low density parity check decoder is operable to scale soft information with a scaling factor in the scaler circuit while iteratively generating and processing check node to variable node messages in the variable node processor and variable node to check node messages in the check node processor between a plurality of check nodes and variable nodes. The scaling factor is derived from a distribution of possible values in an input to the low density parity check decoder.

    Abstract translation: 公开了一种数据处理系统，包括具有可变节点处理器的低密度奇偶校验解码器，校验节点处理器和缩放器电路。 低密度奇偶校验解码器可用于在缩放器电路中缩放具有缩放因子的软信息，同时在可变节点处理器和变量节点中对可变节点消息进行迭代生成并处理校验节点，以校验校验节点处理器中的节点消息 多个检查节点和可变节点。 缩放因子是从低密度奇偶校验解码器的输入中的可能值的分布导出的。

    Decoding System and Method for Electronic Non-Volatile Computer Storage Apparatus
    50.
    发明申请
    Decoding System and Method for Electronic Non-Volatile Computer Storage Apparatus 有权
    电子非易失性计算机存储设备的解码系统和方法

    公开(公告)号：US20150227403A1

    公开(公告)日：2015-08-13

    申请号：US14200659

    申请日：2014-03-07

    Applicant: LSI CORPORATION

    Inventor： Fan Zhang ,  Yu Chin Fabian Lim ,  Shu Li

    IPC: G06F11/07

    CPC classification number: G11C11/5642 ,  G06F11/1008 ,  G06F11/1012 ,  H03M13/1105 ,  H03M13/3723 ,  H03M13/373 ,  H03M13/451 ,  H03M13/6325

    Abstract: Methods are systems for calculating log-likelihood ratios for a decoder utilized in an electronic non-volatile computer storage apparatus are disclosed. A log-likelihood ratio handler is configured to provide an input log-likelihood ratio to the decoder, wherein the input log-likelihood ratio is one of: a uniform input log-likelihood ratio for all bits calculated based on an estimated raw bit error rate for a particular data unit, or a bit-based input log-likelihood ratio for each bit calculated based on a confidence value for a cell containing said each bit. The decoder of the electronic non-volatile computer storage apparatus is configured to decode encoded data at least partially based on the input log-likelihood ratio from the log-likelihood ratio handler.

    Abstract translation: 方法是公开了用于计算在电子非易失性计算机存储装置中使用的解码器的对数似然比的系统。 对数似然比处理器被配置为向解码器提供输入对数似然比，其中输入对数似然比是以下之一：基于估计的原始误码率计算的所有比特的均匀输入对数似然比 或针对包含所述每个位的单元的置信度值计算的每个位的基于位的输入对数似然比。 电子非易失性计算机存储装置的解码器被配置为至少部分地基于来自对数似然比处理器的输入对数似然比来解码编码数据。

Patent Agency Ranking