公开(公告)号：US07457625B2

公开(公告)日：2008-11-25

申请号：US10679818

申请日：2003-10-06

申请人： William R. Krenik ,  Carl M. Panasik

发明人： William R. Krenik ,  Carl M. Panasik

IPC分类号： H04Q7/20

CPC分类号： H04W28/14 ,  H04L1/0023 ,  H04W8/22 ,  H04W8/245 ,  H04W16/14 ,  H04W28/12 ,  H04W48/08 ,  H04W76/10 ,  H04W88/06 ,  H04W92/16

摘要： Wirelessly-linked, distributed resource control (RCS1-RCSn, RCSB, RCC, ARM) supports a wireless communication system (50) for operation in non-exclusive spectrum (24-29). An available resource map (ARM) contains resource availability information gathered by mobile stations (MS1-MSn), and a wired communication channel supports sharing of resource control information among fixed-site stations (BS).

摘要翻译： 无线连接的分布式资源控制（RCS 1 -RCSn，RCSB，RCC，ARM）支持无线通信系统（50），用于在非专有频谱（24-29）中操作。 可用资源图（ARM）包含由移动站（MS 1 -MSn）收集的资源可用性信息，有线通信信道支持在固定站点（BS）之间共享资源控制信息。

公开(公告)号：US20070200927A1

公开(公告)日：2007-08-30

申请号：US11679564

申请日：2007-02-27

申请人： William R. Krenik

发明人： William R. Krenik

IPC分类号： H04N13/02

CPC分类号： A61H5/005 ,  A61B3/0033 ,  A61B3/024 ,  A61B3/032 ,  A61B3/036 ,  A61B3/08 ,  A61H23/02 ,  A61H2201/0207 ,  A61H2201/10 ,  A61H2201/1604 ,  A61H2201/165 ,  A61H2201/501 ,  A61H2201/5043 ,  A61H2201/5048 ,  A61H2201/5058 ,  A61H2201/5092 ,  A61H2201/5097

摘要： A binocular viewer, a method of measuring and training vision that uses a binocular viewer and a vision measurement and training system that employs a computer to control the binocular viewer. In one embodiment, the binocular viewer has left and right display elements and comprises: (1) a variable focal depth optical subsystem located in an optical path between the display elements and a user when the user uses the binocular viewer and (2) a control input coupled to the left and right display elements and the variable focal depth optical subsystem and configured to receive control signals operable to place images on the left and right display elements and vary a focal depth of the variable focal depth optical subsystem. In another embodiment, the binocular viewer lacks the variable focal depth optical subsystem, but the images include at least one feature unique to one of the left and right display elements.

摘要翻译： 双眼观察者，使用双目观察者的测量和训练视觉的方法以及采用计算机来控制双目观察者的视觉测量和训练系统。 在一个实施例中，双目观察器具有左右显示元件，并且包括：（1）当用户使用双目观察者时，位于显示元件与用户之间的光路中的可变焦深光学子系统，以及（2）控制 输入，耦合到左和右显示元件和可变焦深度光学子系统，并且被配置为接收可操作以将图像放置在左显示元件和右显示元件上并改变可变焦深光学子系统的焦深的控制信号。 在另一个实施例中，双目观察器缺少可变焦深度光学子系统，但是图像包括左和右显示元件之一唯一的至少一个特征。

公开(公告)号：US5867001A

公开(公告)日：1999-02-02

申请号：US925242

申请日：1997-09-08

申请人： Rolf Lagerquist ,  William R. Krenik ,  Kenneth J. Maggio ,  Patrick G. O'Farrell

发明人： Rolf Lagerquist ,  William R. Krenik ,  Kenneth J. Maggio ,  Patrick G. O'Farrell

IPC分类号： G01R19/00 ,  H02P6/00 ,  H02P6/10 ,  H02P7/00

CPC分类号： H02P6/10 ,  H02P6/28

摘要： A motor driver circuit (12) for providing drive signals to stator coils of a polyphase dc motor (10) includes a plurality of current paths, each connected between a supply voltage and a reference potential. Each current path includes two driver transistors (14,20, 16,22, 18,24), a node (A, B, C) of each of the stator coils being connectable between the driver transistors in respective current flow paths. A commutator (26) is connected to operate the driver transistors in a sequence in which drive currents are delivered for application in a predetermined sequence to the stator coils. A plurality of sensing transistors (32) are connected to produce a mirror current which mirrors a mirrored current in an associated driver transistor (20) in a respective current flow path. Circuitry (26) is provided which is responsive to the mirror currents of the sensing transistors to control the amplitudes of the currents in the associated driver transistor in a respective current flow path. At least one trim transistor (51-55) is connected in parallel with a respective one of the sensing transistors (50), and a programmable circuit (48) is connected to selectively activate the at least one trim transistor to adjust the amplitudes of the mirrored currents in the current flow path with which the sensing transistor with which the at least one trim transistor is associated.

摘要翻译： 用于向多相直流电动机（10）的定子线圈提供驱动信号的电机驱动器电路（12）包括多个电流路径，每个电流路径连接在电源电压和参考电位之间。 每个电流路径包括两个驱动器晶体管（14,20,16,22,18,24），每个定子线圈的节点（A，B，C）可在相应的电流流动路径中的驱动器晶体管之间连接。 换向器（26）被连接以按驱动电流被输送的顺序来操作驱动器晶体管，以便以预定顺序施加到定子线圈。 连接多个感测晶体管（32）以产生镜电流，其反映相应的电流流动路径中相关联的驱动晶体管（20）中的镜像电流。 提供电路（26），其响应于感测晶体管的镜像电流来控制相应的电流流动路径中相关联的驱动器晶体管中的电流的幅度。 至少一个微调晶体管（51-55）与感测晶体管（50）中的相应一个并联连接，并且可编程电路（48）被连接以选择性地激活所述至少一个修整晶体管以调整 电流流动路径中与至少一个修整晶体管相关联的感测晶体管的镜像电流。

公开(公告)号：US5699087A

公开(公告)日：1997-12-16

申请号：US333899

申请日：1994-11-03

申请人： William R. Krenik ,  Louis J. Izzi

发明人： William R. Krenik ,  Louis J. Izzi

IPC分类号： G09G5/06 ,  G06F12/00

CPC分类号： G09G5/06

摘要： A method is provided for accessing data stored in memory (76). First data appearing at outputs (102) of memory (76) are read during a first reading cycle in a sequence of reading cycles, the first data retrieved from a first location in memory (76) corresponding to a first address. At the end of the first reading cycle, the first address is stepped to produce a second address corresponding to a second location in memory (76). During an idle period following the first reading cycle and prior to a second reading cycle occurring next in the sequence of reading cycles, second data is prefetched from the second location in memory (76) such that the second data appears at the bitlines (102) of memory (76) at the start of the second reading cycle.

摘要翻译： 提供一种访问存储在存储器（76）中的数据的方法。 在第一读取周期期间以读取周期的顺序读出出现在存储器（76）的输出端（102）的第一数据，从存储器（76）中对应于第一地址的第一位置检索的第一数据。 在第一读取周期结束时，第一地址被步进以产生对应于存储器（76）中的第二位置的第二地址。 在第一读取周期之后的空闲时段期间和接下来在读取周期序列中发生第二读取周期之前，从存储器（76）中的第二位置预取第二数据，使得第二数据出现在位线（102）处， 的存储器（76）在第二读取周期的开始。

公开(公告)号：US5693577A

公开(公告)日：1997-12-02

申请号：US632032

申请日：1996-04-12

申请人： William R. Krenik ,  Mark Appleton

发明人： William R. Krenik ,  Mark Appleton

IPC分类号： G01N27/12 ,  H01L21/22

CPC分类号： G01N27/12 ,  Y10S148/035 ,  Y10S148/052

摘要： A sensor 20 is formed on semiconductor substrate 22. Dielectric layers 23 and 24 are formed on the face and backside of substrate 22, respectively. Metal leads 26 and 28 contact the substrate through openings in the dielectric layer 23. The leads 26 and 28 are also connected to the set of interleaved longitudinal contact fingers 27 and 29. Additionally, a pair of backside contacts 30 and 32 are formed on the dielectric layer 24. The backside contact 30 is in contact only with the metal lead 26 through a conductive region 34.

摘要翻译： 传感器20形成在半导体衬底22上。电介质层23和24分别形成在衬底22的表面和背面上。 金属引线26和28通过介质层23中的开口接触基板。引线26和28也连接到一组交错的纵向接触指27和29.另外，一对背侧触点30和32形成在 电介质层24.背面触点30仅通过导电区域34与金属引线26接触。

公开(公告)号：US5650950A

公开(公告)日：1997-07-22

申请号：US455867

申请日：1995-05-31

申请人： Patrick P. Siniscalchi ,  William R. Krenik ,  Michael D. Aragon

发明人： Patrick P. Siniscalchi ,  William R. Krenik ,  Michael D. Aragon

IPC分类号： H03H17/02 ,  G06J1/00

CPC分类号： H03H17/0294

摘要： A programmable, electronic filter (10) includes a memory device such as a Read Only Memory ROM (22) for storing specific cut-off frequency adjustment data corresponding to various cut-off frequencies. The ROM (22) receives a ROM address (28) corresponding to a cut-off frequency signal (26). The ROM (22) generates a specific cut-off frequency adjustment value (30) for a digital-to-analog convertor (20) to produce an output reference current (34). A reference voltage (40), an error amplifier (14), a master transconductance element (16), and a capacitor (18) serve as a tuning loop and ultimately produce a control signal (38) in response to the output reference current (34). Control signal (38) serves as an input to slave filter (12) along with the cut-off frequency signal (26). The slave filter (12) may then serve as an electronic filter having the desired frequency-response characteristic. The slave filter (12) may then receive a slave filter input signal (44) and provide a filtered output signal (46) having an accurate frequency-response characteristic at the desired cut-off frequency.

摘要翻译： 可编程电子滤波器（10）包括诸如只读存储器ROM（22）的存储器件，用于存储对应于各种截止频率的特定截止频率调节数据。 ROM（22）接收对应于截止频率信号（26）的ROM地址（28）。 ROM（22）产生用于数模转换器（20）的特定截止频率调整值（30）以产生输出参考电流（34）。 参考电压（40），误差放大器（14），主跨导元件（16）和电容器（18）用作调谐回路，并且响应于输出参考电流（38）最终产生控制信号（38） 34）。 控制信号（38）与截止频率信号（26）一起用作从滤波器（12）的输入。 然后，从滤波器（12）可以用作具有期望的频率响应特性的电子滤波器。 然后，从滤波器（12）可接收从滤波器输入信号（44），并提供具有所需截止频率的精确频率响应特性的滤波输出信号（46）。

公开(公告)号：US5623265A

公开(公告)日：1997-04-22

申请号：US188299

申请日：1994-01-28

申请人： Vivek J. Pawar ,  William R. Krenik

发明人： Vivek J. Pawar ,  William R. Krenik

IPC分类号： G06F3/05 ,  H03M7/16 ,  H03M1/36

CPC分类号： H03M7/165

摘要： A flash analog-to-digital converter (8) is provided which includes a comparator array (10) which provides a thermometer code output THC1 through THC7. A binary search encoder (12) is coupled to the comparator array (8) as shown, and provides a binary code output B2 through B0.

摘要翻译： 提供一种闪存模数转换器（8），其包括提供温度计代码输出THC1至THC7的比较器阵列（10）。 如图所示，二进制搜索编码器（12）耦合到比较器阵列（8），并且通过B0提供二进制码输出B2。

公开(公告)号：US5528179A

公开(公告)日：1996-06-18

申请号：US455815

申请日：1995-05-31

申请人： Patrick P. Siniscalchi ,  William R. Krenik

发明人： Patrick P. Siniscalchi ,  William R. Krenik

IPC分类号： H03G1/00 ,  H03H11/04 ,  G06G7/12

CPC分类号： H03G1/0023 ,  H03H11/0433 ,  H03H11/0472

摘要： A constant capacitance programmable transconductance input stage (36) includes a first transconductance device (50), second transconductance device (52), and first switch (44) for providing a programmable input stage with a constant input capacitance. The first transconductance device (50) has two inputs and the second transconductance device (52) has two inputs. A first positive input (22) couples directly to one input of the first transconductance device (50) while a first negative input (23) couples directly to one input of the second transconductance device (52). The first positive input (22) and the first negative input (23) are switchably coupled to the remaining inputs of first transconductance device (50) and second transconductance device (52). Depending on the configuration of the first switch (44), either both transconductance devices contribute to the overall transconductance of constant capacitance programmable transconductance input stage (36) or neither does. In either event, the input capacitance remains constant.

摘要翻译： 恒定电容可编程跨导输入级（36）包括第一跨导器件（50），第二跨导器件（52）和用于向可编程输入级提供恒定输入电容的第一开关（44）。 第一跨导器件（50）具有两个输入端，第二跨导器件（52）具有两个输入端。 第一正输入端（22）直接耦合到第一跨导器件（50）的一个输入端，而第一负输入端（23）直接耦合到第二跨导器件（52）的一个输入端。 第一正输入（22）和第一负输入（23）可切换地耦合到第一跨导器件（50）和第二跨导器件（52）的剩余输入。 根据第一开关（44）的配置，两个跨导器件都有助于恒定电容可编程跨导输入级（36）的整体跨导，或者也不参与。 在任一情况下，输入电容保持恒定。

公开(公告)号：US5465058A

公开(公告)日：1995-11-07

申请号：US339057

申请日：1994-11-14

申请人： William R. Krenik ,  Louis J. Izzi

发明人： William R. Krenik ,  Louis J. Izzi

IPC分类号： H03K17/16 ,  H03K19/0175 ,  H03K19/094

CPC分类号： H03K17/164

摘要： An integrated circuit buffer includes a source follower output transistor having an output and also connected by a voltage dropping circuit to a supply rail thereby introducing a controlled amount of Miller effect capacitance in the source follower output transistor. The buffer also has a common source output transistor and a unidirectional conducting circuit connecting between the common source output transistor and the source follower output transistor. Other buffers, palette devices, computer graphics systems and methods are also disclosed.

摘要翻译： 集成电路缓冲器包括具有输出的源极跟随器输出晶体管，并且还通过降压电路连接到电源轨，从而在源极跟随器输出晶体管中引入受控量的米勒效应电容。 缓冲器还具有公共源极输出晶体管和连接在共源极输出晶体管和源极跟随器输出晶体管之间的单向导通电路。 还公开了其他缓冲器，调色板装置，计算机图形系统和方法。

公开(公告)号：US5365126A

公开(公告)日：1994-11-15

申请号：US127213

申请日：1993-09-27

申请人： William R. Krenik ,  Louis J. Izzi

发明人： William R. Krenik ,  Louis J. Izzi

IPC分类号： H03K17/16 ,  H03K19/092 ,  H03K19/094

CPC分类号： H03K17/164

摘要： An integrated circuit buffer includes a source follower output transistor having an output and also connected by a voltage dropping circuit to a supply rail thereby introducing a controlled amount of Miller effect capacitance in the source follower output transistor. The buffer also has a common source output transistor and a unidirectional conducting circuit connecting between the common source output transistor and the source follower output transistor. Other buffers, palette devices, computer graphics systems and methods are also disclosed.

摘要翻译： 集成电路缓冲器包括具有输出的源极跟随器输出晶体管，并且还通过降压电路连接到电源轨，从而在源极跟随器输出晶体管中引入受控量的米勒效应电容。 缓冲器还具有公共源极输出晶体管和连接在共源极输出晶体管和源极跟随器输出晶体管之间的单向导通电路。 还公开了其他缓冲器，调色板装置，计算机图形系统和方法。