公开(公告)号：US20160190151A1

公开(公告)日：2016-06-30

申请号：US14584416

申请日：2014-12-29

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chin-Cheng Yang

IPC: H01L27/115

CPC classification number: H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578

Abstract: Disclosed herein are semiconductor devices and methods for fabricating a semiconductor device. In an embodiment, a method of fabricating a semiconductor device comprises providing a substrate. The method further comprises forming, on the substrate, an array region having a first height, a peripheral region having a second height greater than the first height, and a border region, the border region separating the array region from the peripheral region. The method further comprises forming a plurality of alternating insulative and conductive layers over at least a portion of the array region and the border region. The method further comprises forming a trench through the plurality of alternating insulative and conductive layers in at least a portion of the border region, the trench having sloping sidewalls.

Abstract translation: 这里公开了用于制造半导体器件的半导体器件和方法。 在一个实施例中，制造半导体器件的方法包括提供衬底。 该方法还包括在衬底上形成具有第一高度的阵列区域，具有大于第一高度的第二高度的周边区域和边界区域，边界区域将阵列区域与周边区域分开。 该方法还包括在阵列区域和边界区域的至少一部分上形成多个交替的绝缘和导电层。 该方法还包括在边界区域的至少一部分中通过多个交替的绝缘和导电层形成沟槽，沟槽具有倾斜的侧壁。

公开(公告)号：US20160155658A1

公开(公告)日：2016-06-02

申请号：US14558267

申请日：2014-12-02

Applicant: MACRONIX International Co., Ltd.

Inventor： Chin-Cheng Yang

IPC: H01L21/687 ,  B25J15/00

CPC classification number: B25J15/009 ,  H01L21/68707

Abstract: A wafer holder and a semiconductor wafer carrying tool including the wafer holder are provided. The wafer holder includes a frame portion, a wafer centering unit and a plurality of support pins for supporting the wafer carried by the wafer holder. The wafer centering unit comprises a plurality of pin cassettes, and the plurality of pin cassettes is arranged on the frame portion in diagonal positions. Each of the plurality of pin cassettes individually includes a retractable pin, and the retractable pins can be protruded out of the pin cassettes to function together as a space limiting tool to force the carried wafer to calibrate its position.

Abstract translation: 提供晶片保持器和包括晶片保持器的半导体晶片承载工具。 晶片保持器包括框架部分，晶片定心单元和用于支撑由晶片保持器承载的晶片的多个支撑销。 晶片定心单元包括多个销盒，并且多个销盒以对角位置布置在框架部分上。 所述多个销盒中的每一个分别包括可缩回销，并且所述可缩回销可以突出到所述销盒中，以一起作为空间限制工具来作用，以迫使承载的晶片校准其位置。

公开(公告)号：US20160086809A1

公开(公告)日：2016-03-24

申请号：US14492969

申请日：2014-09-22

Applicant: MACRONIX International Co., Ltd.

Inventor： Chin-Cheng Yang

IPC: H01L21/308 ,  H01L21/311

CPC classification number: H01L21/3088 ,  H01L21/3086 ,  H01L21/31105 ,  H01L21/31127 ,  H01L21/32139

Abstract: A patterning method is provided. A substrate including a material layer thereon is provided. A patterned hard mask layer, having a plurality of first holes, is formed on the material layer. Afterward, a mask layer, including a plurality of line pattern masks extending in a direction and dividing each first hole into a second hole and a third hole, is formed. The material layer is patterned using the patterned hard mask layer and the mask layer as masks to form a patterned material layer having a plurality of fourth and fifth holes. Furthermore, a semiconductor structure is provided.

Abstract translation: 提供了图案化方法。 提供了包括其上的材料层的基板。 在材料层上形成具有多个第一孔的图案化的硬掩模层。 之后，形成包括在一个方向上延伸并将每个第一孔分成第二孔和第三孔的多个线图案掩模的掩模层。 使用图案化的硬掩模层和掩模层作为掩模来图案化材料层，以形成具有多个第四和第五孔的图案化材料层。 此外，提供了半导体结构。

公开(公告)号：US20160071867A1

公开(公告)日：2016-03-10

申请号：US14478626

申请日：2014-09-05

Applicant: MACRONIX International Co., Ltd.

Inventor： Chin-Cheng Yang

IPC: H01L27/115 ,  H01L21/3213 ,  H01L21/28 ,  H01L21/311

CPC classification number: H01L27/11582 ,  H01L21/31144 ,  H01L21/32139 ,  H01L27/11575

Abstract: Provided is a semiconductor device including a substrate and a stack layer. The substrate includes a first region, a second region, and a third region. The third region is disposed between the first region and the second region. Since a top surface of the substrate in the first region is lower than the top surface of the substrate in the second region, the substrate in the third region has a first step height. The stack layer is disposed on the substrate in the first and third regions. The top surface of the stack layer in the first region and the third region and the top surface of the substrate in the second region are substantially coplanar.

Abstract translation: 提供了包括基板和堆叠层的半导体器件。 衬底包括第一区域，第二区域和第三区域。 第三区域设置在第一区域和第二区域之间。 由于第一区域中的基板的顶表面比第二区域中的基板的顶表面低，所以第三区域中的基板具有第一台阶高度。 堆叠层在第一和第三区域中设置在基板上。 第一区域中的堆叠层的顶表面和第二区域中的第三区域和衬底的顶表面基本上共面。

公开(公告)号：US20160048087A1

公开(公告)日：2016-02-18

申请号：US14457982

申请日：2014-08-12

Applicant: MACRONIX International Co., Ltd.

Inventor： Chin-Cheng Yang ,  Chi-Hao Huang

IPC: G03F7/20

CPC classification number: G03F7/707 ,  G03F7/70633 ,  G03F7/70708 ,  G03F7/70783 ,  G03F9/7011 ,  H01L21/682

Abstract: A scanner and a method for performing an exposure process through a photomask on a wafer are provided. The exposure process includes an alignment step and an exposure step. The method includes the steps of moving a wafer table to align the wafer with an alignment apparatus, wherein the wafer table includes at least one chuck hole to attach the wafer to the wafer table by vacuum chucking, detecting an actual position of each of a plurality of alignment marks on the wafer, calculating an index value based on a difference between a predicted position and the actual position of each alignment mark, adjusting a vacuum pressure of the at least one chuck hole in the alignment step when the index value is larger than a first threshold value, and finishing the exposure process when the index value is smaller than or equal to the first threshold value.

Abstract translation: 提供了扫描仪和通过晶片上的光掩模进行曝光处理的方法。 曝光过程包括对准步骤和曝光步骤。 该方法包括以下步骤：移动晶片台以使晶片与对准装置对准，其中晶片台包括至少一个卡盘孔，以通过真空夹紧将晶片附接到晶片台，检测多个实体中的每一个的实际位置 在所述晶片上的对准标记，基于预测位置和每个对准标记的实际位置之间的差异来计算指标值，当所述指标值大于所述对准步骤时，调整所述对准步骤中的所述至少一个卡盘孔的真空压力 第一阈值，并且当所述指标值小于或等于所述第一阈值时完成所述曝光处理。