公开(公告)号：US11222690B2

公开(公告)日：2022-01-11

申请号：US16725261

申请日：2019-12-23

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu ,  Karthik Sarpatwari ,  Durai Vishak Nirmal Ramaswamy

IPC: G11C7/00 ,  G11C11/4097 ,  G11C11/4096 ,  H01L27/108 ,  G11C11/4094

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes multiple levels of two-transistor (2T) memory cells vertically arranged above a substrate. Each 2T memory cell includes a charge storage transistor having a gate, a write transistor having a gate, a vertically extending access line, and a single bit line pair. The source or drain region of the write transistor is directly coupled to a charge storage structure of the charge storage transistor. The vertically extending access line is coupled to gates of both the charge storage transistor and the write transistor of 2T memory cells in multiple respective levels of the multiple vertically arranged levels. The vertically extending access line and the single bit line pair are used for both write operations and read operations of each of the 2T memory cells to which they are coupled.

公开(公告)号：US20210391461A1

公开(公告)日：2021-12-16

申请号：US17446362

申请日：2021-08-30

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Durai Vishak Nimal Ramaswamy ,  Haitao Liu

IPC: H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: A device comprises a first conductive line and a vertical transistor over the first conductive line. The vertical transistor comprises a gate electrode, a gate dielectric material overlying sides of the gate electrode, and a channel region on sides of the gate dielectric material, the gate dielectric material located between the channel region and the gate electrode. The device further comprises a second conductive line overlying a conductive contact of the at least one vertical transistor. Related devices and methods of forming the devices are also disclosed.

公开(公告)号：US20210384354A1

公开(公告)日：2021-12-09

申请号：US16891462

申请日：2020-06-03

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Guangyu Huang ,  Haitao Liu ,  Akira Goda

IPC: H01L29/786 ,  H01L29/66 ,  H01L27/11573 ,  H01L27/11529

Abstract: A transistor comprises a lower contact structure, a channel structure, a dielectric fill structure, and an upper contact structure. The lower contact structure comprises a first oxide semiconductive material. The channel structure contacts the lower contact structure and comprises a second oxide semiconductive material having a smaller atomic concentration of one or more metals than the first oxide semiconductive material. The dielectric fill structure contacts an inner side surface of the channel structure and has a recessed upper surface relative to the channel structure. The upper contact structure comprises a third oxide semiconductive material having a greater atomic concentration of the one or more metals than the channel structure. The upper contact structure comprises a first portion contacting the upper surface of the dielectric fill structure and the inner side surface of the channel structure, and a second portion contacting the upper surface of the channel structure.

公开(公告)号：US20210265467A1

公开(公告)日：2021-08-26

申请号：US17317668

申请日：2021-05-11

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Deepak Chandra Pandey ,  Haitao Liu ,  Richard J. Hill ,  Guangyu Huang ,  Yunfei Gao ,  Ramanathan Gandhi ,  Scott E. Sills

IPC: H01L29/267 ,  H01L29/786 ,  H01L27/108 ,  H01L29/207 ,  H01L29/08 ,  H01L29/16

Abstract: Some embodiments include an integrated assembly having a polycrystalline first semiconductor material, and having a second semiconductor material directly adjacent to the polycrystalline first semiconductor material. The second semiconductor material is of a different composition than the polycrystalline first semiconductor material. A conductivity-enhancing dopant is within the second semiconductor material. The conductivity-enhancing dopant is a neutral-type dopant relative to the polycrystalline first semiconductor material. An electrical gate is adjacent to a region of the polycrystalline first semiconductor material and is configured to induce an electric field within said region of the polycrystalline first semiconductor material. The gate is not adjacent to the second semiconductor material.

公开(公告)号：US11043260B2

公开(公告)日：2021-06-22

申请号：US16722665

申请日：2019-12-20

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu ,  Karthik Sarpatwari ,  Durai Vishak Nirmal Ramaswamy

IPC: G11C11/40 ,  G11C11/4096 ,  H01L27/108 ,  G11C11/4094

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes multiple two-transistor (2T) memory cells. Each of the multiple 2T memory cells includes: a p-channel field effect transistor (PFET) including a charge storage node and a read channel portion, an n-channel field effect transistor (NFET) including a write channel portion that is directly coupled to the charge storage node of the PFET; a single bit line pair coupled to the read channel portion of the PFET; and a single access line overlapping at least part of each of the read channel portion and the write channel portion.

公开(公告)号：US20210183951A1

公开(公告)日：2021-06-17

申请号：US17182953

申请日：2021-02-23

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy

IPC: H01L27/24 ,  G11C13/00 ,  H01L27/12 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L45/00 ,  H01L29/786

Abstract: Methods of forming a semiconductor device are disclosed. A method comprising forming a hybrid transistor supported by a substrate. Forming the hybrid transistor comprises forming a source including a first low bandgap high mobility material, and forming a channel including a high bandgap low mobility material coupled with the first low bandgap high mobility material. Forming the hybrid transistor further comprises forming a drain including a second low bandgap high mobility material coupled with the a high bandgap low mobility material, and forming a gate separated from the channel via a gate oxide material. Methods of forming a transistor are also disclosed.

公开(公告)号：US20210066135A1

公开(公告)日：2021-03-04

申请号：US16558928

申请日：2019-09-03

Applicant: Micron Technology, Inc.

Inventor： Deepak Chandra Pandey ,  Haitao Liu ,  Kamal M. Karda

IPC: H01L21/8234 ,  H01L29/08 ,  H01L23/528 ,  H01L29/10 ,  H01L29/78 ,  H01L27/1159 ,  H01L27/11507

Abstract: An array of vertical transistors comprises spaced pillars individually comprising a channel region of individual vertical transistors. A horizontally-elongated conductor line directly electrically couples together individual of the channel regions of the pillars of a plurality of the vertical transistors. An upper source/drain region is above the individual channel regions of the pillars, a lower source/drain region is below the individual channel regions of the pillars, and a conductive gate line is operatively aside the individual channel regions of the pillars and that interconnects multiple of the vertical transistors. Methods are disclosed.

公开(公告)号：US20210013305A1

公开(公告)日：2021-01-14

申请号：US16509093

申请日：2019-07-11

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu ,  Si-Woo Lee ,  Fatma Arzum Simsek-Ege ,  Deepak Chandra Pandey ,  Chandra V. Mouli ,  John A. Smythe, III

IPC: H01L29/06 ,  H01L27/108 ,  H01L21/762

Abstract: An example apparatus includes a first source/drain region and a second source/drain region formed in a substrate to form an active area of the apparatus. The first source/drain region and the second source/drain region are separated by a channel. The apparatus includes a gate opposing the channel. A sense line is coupled to the first source/drain region and a storage node is coupled to the second source/drain region. An isolation trench is adjacent to the active area. The trench includes a dielectric material with a conductive bias opposing the conductive bias of the channel in the active area.

公开(公告)号：US20200295005A1

公开(公告)日：2020-09-17

申请号：US16298947

申请日：2019-03-11

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Yi Fang Lee ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy ,  Ramanathan Gandhi ,  Karthik Sarpatwari ,  Scott E. Sills ,  Sameer Chhajed

IPC: H01L27/105 ,  H01L27/092 ,  H01L27/12 ,  H01L29/24 ,  H01L29/267 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66

Abstract: Some embodiments include an integrated assembly having a first semiconductor material between two regions of a second semiconductor material. The second semiconductor material is a different composition than the first semiconductor material. Hydrogen is diffused within the first and second semiconductor materials. The conductivity of the second semiconductor material increases in response to the hydrogen diffused therein to thereby create a structure having the second semiconductor material as source/drain regions, and having the first semiconductor material as a channel region between the source/drain regions. A transistor gate is adjacent the channel region and is configured to induce an electric field within the channel region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US10777281B2

公开(公告)日：2020-09-15

申请号：US16227874

申请日：2018-12-20

Applicant: Micron Technology, Inc.

Inventor： Guangyu Huang ,  Haitao Liu ,  Akira Goda

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/10 ,  H01L27/11524 ,  H01L27/11573 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11529 ,  G11C16/16 ,  H01L27/11565 ,  H01L27/11575 ,  G11C7/10

Abstract: Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a first group of conductive materials interleaved with a first group of dielectric materials, a first pillar extending through the first group of conductive materials and the first group of dielectric materials, memory cells located along the first pillar, a conductive contact coupled to one of the conductive materials, and a second pillar extending through a second group of conductive materials and a second group of dielectric materials. The second pillar includes a first portion coupled to a conductive region, a second portion, and a third portion, and a fourth portion coupled to the conductive contact. The second portion is located between the first and third portions. The second portion has a doping concentration less than a doping concentration of each of the first and fourth portions.