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41.发明授权Frequency control circuit, motor drive apparatus, frequency control method, control method of motor drive apparatus, and program allowing computer to execute control method 有权频率控制电路，电机驱动装置，频率控制方法，电动机驱动装置的控制方法以及允许计算机执行控制方法的程序公开(公告)号：US07317291B2
公开(公告)日：2008-01-08
申请号：US11552407
申请日：2006-10-24
申请人： Akio Atsuta , Shinichi Yamashita
发明人： Akio Atsuta , Shinichi Yamashita
IPC分类号： H02P1/00
CPC分类号： H02N2/008
摘要： A frequency control circuit including a control circuit for setting a set value, an adding circuit for adding the set value per unit time and effecting counting based on the adding result, and a signal output circuit for outputting an alternating signal of a cycle corresponding to the time necessary for the count result by the adding circuit to reach a target value. The control circuit sets the set value as a value which does not correspond to a submultiple of the target value, and the adding circuit starts the counting of a next cycle when the count result reaches the target value. The control circuit further sets an initial value of the counting of the next cycle in accordance with a value of a portion of the adding results, exceeding the target value when the count result reaches the target value.
摘要翻译： 一种频率控制电路，包括用于设定设定值的控制电路，加法电路，用于将每单位时间的设定值相加，并根据相加结果进行计数;以及信号输出电路，输出与 由加法电路达到目标值的计数结果所需的时间。 控制电路将设定值设定为不对应于目标值的多项的值，并且当计数结果达到目标值时，加法电路开始下一个周期的计数。 当计数结果达到目标值时，控制电路还根据加法结果的一部分的值来设定下一周期的计数的初始值，超过目标值。
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公开(公告)号：US6137835A
公开(公告)日：2000-10-24
申请号：US920865
申请日：1997-08-29
CPC分类号： H04N19/59 , H04N19/112 , H04N19/119 , H04N19/80 , H04N19/137
摘要： A picture coding apparatus includes a first compressing device for offset sampling input signals, and a second compressing device, having at an orthogonal transform circuit and a quantization device, for compressing the output from the first compressing device, wherein the quantization levels of the quantization device are set so that high-frequency components along a predetermined direction are quantized precisely on the basis of the visibility of each frequency component discriminated by orthogonal transform on a display screen.
摘要翻译： 图像编码装置包括用于偏移采样输入信号的第一压缩装置和在正交变换电路和量化装置处具有用于压缩来自第一压缩装置的输出的第二压缩装置，其中量化装置的量化级 被设置为使得基于在正交变换识别的每个频率分量的可视性在显示屏幕上精确量化沿着预定方向的高频分量。
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43.发明授权Apparatus for generating a signal whose phase is synchronized with an inputted digital signal 失效用于产生其相位与输入的数字信号同步的信号的装置
公开(公告)号：US6118606A
公开(公告)日：2000-09-12
申请号：US939679
申请日：1997-09-29
CPC分类号： G11B20/1403 , H03L7/091 , H04N5/93
摘要： A specific pattern in an inputted digital signal is detected and the input digital signal is sampled and held in accordance with such a detection output. A clock whose phase is synchronized with the input digital signal is generated on the basis of the sampling output. With such a construction as mentioned above, the phase of the clock can be optimally controlled by a simple construction. The clock can be precisely extracted from the input digital signal, so that the operation of a circuit is also stable.
摘要翻译： 检测输入数字信号中的特定模式，并根据这种检测输出对输入数字信号进行采样和保持。 基于采样输出产生与输入数字信号同步的时钟。 通过上述这样的结构，可以通过简单的结构来最佳地控制时钟的相位。 可以从输入数字信号中精确地提取时钟，使电路的运行也稳定。
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公开(公告)号：US6091294A
公开(公告)日：2000-07-18
申请号：US150564
申请日：1998-09-10
CPC分类号： H03F3/347
摘要： An amplifier circuit for amplifying an input signal and outputting the amplified signal includes a first amplifier for outputting from a first output terminal a current proportional to a difference voltage between voltages at a first input terminal and a second input terminal, and a second amplifier for outputting from a second output terminal a current proportional to a difference voltage between voltages at the first input terminal and the second input terminal and for feeding back a current outputted from the second output terminal to the second input terminal, so that the amplifier circuit is operable at a supply voltage of 3 V.
摘要翻译： 用于放大输入信号并输出放大信号的放大器电路包括：第一放大器，用于从第一输出端输出与第一输入端和第二输入端之间的电压之间的差分电压成正比的电流;以及第二放大器，用于输出 从第二输出端子输出与第一输入端子和第二输入端子处的电压之间的差分电压成比例的电流，并将从第二输出端子输出的电流反馈到第二输入端子，使得放大器电路可操作在 电源电压为3 V.
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45.发明授权Multichannel digital-signal reproducing apparatus for switching access timing relative to reproducing timing based on a determination of recorded/reproduced information 失效多通道数字信号再现装置，用于基于记录/再现信息的确定来切换与再现定时相关的存取定时
公开(公告)号：US5790746A
公开(公告)日：1998-08-04
申请号：US478658
申请日：1995-06-07
IPC分类号： G11B15/467 , G11B20/10 , G11B20/12 , G11B20/18 , G11B27/30 , H04N5/7826 , H04N9/797 , H04N9/877 , H04N9/888 , H04N5/911
CPC分类号： H04N5/78266 , G11B15/4678 , G11B20/10 , G11B20/10527 , G11B20/1833 , G11B27/3009 , G11B27/3027 , H04N9/7973 , H04N9/877 , H04N9/888 , G11B20/1208 , G11B2020/10592 , G11B2220/90
摘要： An apparatus for reproducing digital information from a recording medium having a plurality of parallel tracks and digital information recorded thereon as n-channel (n being an integer greater than or equal to 2) digital signals. The n-channel digital signals are reproduced by n-reproducing heads. The digital information contained in the reproduced signals is stored in a storage device. Discriminating data is obtained for determining which of the n-channel digital signals reproduced correspond to the reproducing heads. The timing of an access device, accessing the storage device for performing a predetermined processing of the digital signals stored in the storage device relative to the reproducing timing of the digital information reproduced by the n reproducing heads, is controlled in accordance with the discrimination data.
摘要翻译： 一种用于从具有多个并行轨道和其上记录的数字信息的记录介质再现数字信息的装置，其中n信道（n是大于或等于2的整数）数字信号。 n路数字信号由n个再现头再现。 包含在再现信号中的数字信息被存储在存储装置中。 获得鉴别数据，用于确定所再现的n路数字信号中的哪一个对应于再现头。 根据鉴别数据控制存取装置的访问存储装置，用于对存储在存储装置中的数字信号进行预定处理，相对于由n个再现头再现的数字信息的再现定时。
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46.发明授权Clock generating circuit by using the phase difference between a burst signal and the oscillation signal 失效通过使用脉冲串信号和振荡信号之间的相位差来产生时钟
公开(公告)号：US5745314A
公开(公告)日：1998-04-28
申请号：US299811
申请日：1994-09-01
申请人： Shingo Ikeda , Shinichi Yamashita
发明人： Shingo Ikeda , Shinichi Yamashita
摘要： A circuit for generating a clock of a predetermined frequency in folllowing-up relation to an input video signal, comprising a PLL circuit including a phase comparison circuit for comparing the phase of a synchronizing signal of the video signal with the phase of a feedback clock corresponding to the clock, and a control circuit for causing the feedback clock in the PLL circuit to be synchronized with the synchronizing signal.
摘要翻译： 一种用于产生与输入视频信号相关的预定频率的时钟的电路，包括一个PLL电路，该PLL电路包括一个相位比较电路，用于将视频信号的同步信号的相位与对应的反馈时钟的相位进行比较 以及用于使PLL电路中的反馈时钟与同步信号同步的控制电路。
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47.发明授权Information recording apparatus which eliminates unnecessary data before recording 失效在记录之前消除不必要的数据的信息记录装置
公开(公告)号：US5544176A
公开(公告)日：1996-08-06
申请号：US250940
申请日：1994-05-31
CPC分类号： H04N1/32379 , G11B20/10 , G11B20/18 , G11B20/1833 , H03M13/00 , H04N1/32363 , H04N9/8715 , H04N2201/3288 , H04N5/85
摘要： An information recording apparatus records data, which is in the format of packets received by broadcast, on a recording medium having a write/read capability. If the received data contains any unnecessary items of data that can be reproduced later, these items of data are eliminated at the time of recording on the recording medium. At playback, the eliminated items of data are restored and appended to the data read in from the recording medium. The resulting data, which is substantially the same as that in the packets received by broadcast, is outputted to a playback apparatus capable of reproducing the broadcast.
摘要翻译： 信息记录装置以具有写入/读取能力的记录介质将通过广播接收的分组的格式的数据记录在记录介质上。 如果接收到的数据包含可以稍后再现的任何不必要的数据项，则在记录介质上记录这些数据的数据。 在回放时，消除的数据项被恢复并附加到从记录介质读入的数据。 与广播接收的分组基本相同的结果数据被输出到能够再现广播的再现装置。
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公开(公告)号：US5528307A
公开(公告)日：1996-06-18
申请号：US395296
申请日：1995-02-27
申请人： Mitsuru Owada , Shinichi Yamashita , Makoto Gohda
发明人： Mitsuru Owada , Shinichi Yamashita , Makoto Gohda
CPC分类号： H04N9/896
摘要： An apparatus for correcting a time base of a video signal generates a clock which is phase-synchronized with a sync. signal of the video signal and has the same frequency. In a special reproducing mode, the apparatus switches an output level of a phase comparator, which phase-compares the sync. signal and the clock to a predetermined level, which is applied to a controlled oscillator and resets a frequency divider which frequency-divides the output of the controlled oscillator, in accordance with the sync. signal to produce the video signal which can be visually recognized even in the special reproducing mode. The apparatus samples and holds the output level of the phase comparator when the video signal drops out and resets the frequency divider which produces the clock by frequency-dividing the output of the controlled oscillator, when the dropout is recovered so that a video signal of high quality is produced immediately after the recovery of the dropout of the video signal.
摘要翻译： 用于校正视频信号的时基的装置产生与同步相位同步的时钟。 视频信号的信号并具有相同的频率。 在特殊再现模式中，该装置切换相位比较器的输出电平，该相位比较器进行相位比较同步。 信号和时钟到预定电平，其被施加到受控振荡器并且根据同步来复位频率划分受控振荡器的输出的分频器。 信号以产生即使在特殊再现模式下也可视觉识别的视频信号。 当视频信号丢失时，该装置采样并保持相位比较器的输出电平，并且通过对受控振荡器的输出进行分频来复位产生时钟的分频器，当压降恢复时，视频信号为高电平 在恢复视频信号的丢失之后立即产生质量。
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公开(公告)号：US5335077A
公开(公告)日：1994-08-02
申请号：US906267
申请日：1992-06-26
申请人： Shinichi Yamashita , Shingo Ikeda , Makoto Gohda
发明人： Shinichi Yamashita , Shingo Ikeda , Makoto Gohda
CPC分类号： H04N9/896
摘要： A time base correcting device inputs a video signal including a sync. signal and a burst signal, produces an error signal representing a phase difference between a clock signal synchronized with the sync. signal and the burst signal, writes the video signal into the memory in synchronism with the clock signal having a phase thereof adjusted in accordance with the error signal, produces an interpolation signal to interpolate a plurality of adjacent error signals along a time base and controls the readout from the memory by the error signals and the interpolation signal. In this manner, it attains time base correction, particularly velocity error correction with high accuracy.
摘要翻译： 时基校正装置输入包括同步的视频信号。 信号和突发信号产生表示与同步同步的时钟信号之间的相位差的误差信号。 信号和突发信号，将视频信号与具有根据误差信号调整的相位的时钟信号同步地写入存储器，产生内插信号，以沿着时基内插多个相邻的误差信号，并且控制 通过误差信号和插值信号从存储器读出。 以这种方式，可以实现时基校正，特别是高精度的速度误差校正。
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公开(公告)号：US5273784A
公开(公告)日：1993-12-28
申请号：US981790
申请日：1992-11-25
申请人： Shinichi Yamashita , Hidefumi Inoue
发明人： Shinichi Yamashita , Hidefumi Inoue
CPC分类号： B05B13/0228
摘要： A method of painting a portion of a shell of a brake booster which is joined together by a caulking operation. A pair of members are disposed in opposing relationship to each other, and a shear caulking operation is applied to the outer periphery thereof at a plurality of locations, thereby joining the members together to define a shell. The shell is held so as to be rotatable about its axis, and a nozzle of a paint applicator is disposed in opposing relationship with the outer periphery of the shell. By intermittently rotating the shell through a given angle, paint is applied successively to only the caulked portions.
摘要翻译： 一种通过铆接操作连接在一起的制动助力器壳体的一部分的涂覆方法。 一对构件彼此相对设置，并且在多个位置处对其外周施加剪切铆接操作，从而将构件接合在一起以限定壳体。 壳体被保持为能够围绕其轴线旋转，并且涂料施加器的喷嘴设置成与壳体的外周相对关系。 通过间歇地旋转壳体一定角度，油漆依次施加到铆接部分。
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