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41.发明授权Memory controllers, memory systems, solid state drives and methods for processing a number of commands 有权存储器控制器，存储器系统，固态驱动器以及用于处理多个命令的方法公开(公告)号：US08055816B2
公开(公告)日：2011-11-08
申请号：US12421093
申请日：2009-04-09
CPC分类号： G06F3/061 , G06F3/0659 , G06F3/067 , G06F3/0679 , G06F3/0688 , G06F13/161 , G06F13/28
摘要： The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.
摘要翻译： 本公开包括用于存储器控制器的方法和装置。 在一个或多个实施例中，存储器控制器包括多个后端通道，以及通信地耦合到多个后端通道的命令队列。 命令队列配置为保存从主机接收的主机命令。 电路被配置为至少响应于命令队列中的主机命令的数量生成多个后端命令，并且将后端命令的数量分配给多个后端信道的数量。
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公开(公告)号：US20100228940A1
公开(公告)日：2010-09-09
申请号：US12397396
申请日：2009-03-04
申请人： Mehdi Asnaashari , Alan Chen , Siamack Nemazie
发明人： Mehdi Asnaashari , Alan Chen , Siamack Nemazie
CPC分类号： G06F12/0246 , G06F2212/7202 , G06F2212/7209 , G11C29/76
摘要： Various embodiments include one or more memory devices having at least two planes of physical blocks organized into super blocks, with each super block including a physical block from each of the at least two planes. Embodiments include determining defective blocks within the planes. If none of the blocks at a particular block position are determined to be defective, embodiments include assigning the blocks at the particular block position to a super block, and if one or more of the blocks at a particular block position are determined to be defective, embodiments include: assigning the blocks at the particular block position determined to be defective to a super block; and assigning a respective replacement block to the super block for each of the one or more blocks at the particular block position determined to be defective. The respective replacement block is selected from a number of blocks within a respective one of the planes that includes the respective block determined to be defective.
摘要翻译： 各种实施例包括具有组织成超块的物理块的至少两个平面的一个或多个存储器件，每个超级块包括来自至少两个平面中的每一个的物理块。 实施例包括确定平面内的有缺陷的块。 如果没有将特定块位置处的块都确定为有缺陷，则实施例包括将特定块位置处的块分配给超块，并且如果确定特定块位置处的一个或多个块被确定为有缺陷， 实施例包括：将确定为有缺陷的特定块位置的块分配给超块; 以及针对被确定为有缺陷的特定块位置处的所述一个或多个块中的每个块为所述超级块分配相应的替换块。 相应的替换块从包括被确定为有缺陷的相应块的平面中的相应一个中的多个块中选择。
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公开(公告)号：US20100211834A1
公开(公告)日：2010-08-19
申请号：US12388305
申请日：2009-02-18
CPC分类号： G06F11/1048 , G06F11/10 , G06F11/1004 , G06F13/28 , G06F21/64 , G11C2029/0411 , H03M13/09 , H03M13/13 , H03M13/29
摘要： The present disclosure includes methods, devices, and systems for data integrity in memory controllers. One memory controller embodiment includes a host interface and first error detection circuitry coupled to the host interface. The memory controller can include a memory interface and second error detection circuitry coupled to the memory interface. The first error detection circuitry can be configured to calculate error detection data for data received from the host interface and to check the integrity of data transmitted to the host interface. The second error detection circuitry can be configured to calculate error correction data for data and first error correction data transmitted to the memory interface and to check integrity of data and first error correction data received from the memory interface.
摘要翻译： 本公开包括用于存储器控制器中的数据完整性的方法，设备和系统。 一个存储器控制器实施例包括耦合到主机接口的主机接口和第一错误检测电路。 存储器控制器可以包括耦合到存储器接口的存储器接口和第二错误检测电路。 第一错误检测电路可以被配置为计算从主机接口接收的数据的错误检测数据，并且检查发送到主机接口的数据的完整性。 第二错误检测电路可以被配置为计算发送到存储器接口的数据和第一纠错数据的纠错数据，并且检查数据的完整性和从存储器接口接收到的第一纠错数据。
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公开(公告)号：US20100185830A1
公开(公告)日：2010-07-22
申请号：US12356765
申请日：2009-01-21
CPC分类号： G06F12/06 , G06F3/0608 , G06F3/0638 , G06F3/0679 , G06F12/0246 , G06F2212/7202
摘要： The present disclosure includes methods, devices, and systems for a logical address offset. One method embodiment includes detecting a memory unit formatting operation. Subsequently, in response to detecting the formatting operation, the method includes inspecting format information on the memory unit, calculating a logical address offset, and applying the offset to a host logical address.
摘要翻译： 本公开包括用于逻辑地址偏移的方法，设备和系统。 一种方法实施例包括检测存储器单元格式化操作。 随后，响应于检测格式化操作，该方法包括检查存储器单元上的格式信息，计算逻辑地址偏移量，以及将偏移量应用于主机逻辑地址。
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45.发明申请SYSTEM AND METHOD FOR SUPPORTING MULTIPLE TOKENS HAVING A SMART CARD TO CONTROL PARAMETERS OF A FLASH MEMORY DEVICE 审中-公开用于支持具有智能卡以控制闪存存储器件的参数的多个功能的系统和方法公开(公告)号：US20090125645A1
公开(公告)日：2009-05-14
申请号：US11938777
申请日：2007-11-12
IPC分类号： G06F3/00
CPC分类号： G06F3/0644 , G06F3/0623 , G06F3/0632 , G06F3/0679 , G06F21/78 , G06F2221/2153
摘要： A system and method to control a device having at least one configurable parameter. Enumerating the device as a first peripheral device and as a second peripheral device wherein the first peripheral device corresponds to a first microcontroller connected to a storage medium and the second peripheral device corresponds to a second microcontroller. Controlling the at least one configurable parameter of the first microcontroller with respect to the storage medium by the second microcontroller. On initialization of the device, transmitting the at least one configurable parameter from the second microcontroller to the first microcontroller. Other systems and methods are disclosed.
摘要翻译： 一种用于控制具有至少一个可配置参数的设备的系统和方法。 将设备列举为第一外围设备和第二外围设备，其中第一外围设备对应于连接到存储介质的第一微控制器，而第二外围设备对应于第二微控制器。 通过第二微控制器控制第一微控制器相对于存储介质的至少一个可配置参数。 在初始化装置时，将至少一个可配置参数从第二微控制器发送到第一微控制器。 公开了其它系统和方法。
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46.发明申请公开(公告)号：US20090121029A1
公开(公告)日：2009-05-14
申请号：US11938734
申请日：2007-11-12
IPC分类号： G06K19/067
CPC分类号： G06F21/44 , G06F13/387 , G06F21/34 , G06F21/77 , G06F21/79 , G06K19/0715 , G06K19/073
摘要： A storage device contains a smart-card device and a memory device, both of which are accessed though a controller. The storage device may be used in the same manner as a conventional smart-card device, or it may be used to store a relatively large amount of data in various partitions corresponding to the protection level of the data stored therein. The smart-card device stores critical security parameters that are provided to the controller to protect access to some or all of the partitions of the memory device. A host connected to the controller issues commands, and the controller analyzes the commands and responds to them in various ways depending upon the nature of the command. In particular, depending upon the nature of the command, the controller may either pass the command to the smart-card device, or ignore the command either indefinitely or until a predetermined event has occurred.
摘要翻译： 存储设备包含智能卡设备和存储设备，两者均通过控制器访问。 存储装置可以以与常规智能卡装置相同的方式使用，或者可以用于将相对大量的数据存储在与其中存储的数据的保护级别相对应的各个分区中。 智能卡设备存储提供给控制器的关键安全参数，以保护对存储设备的某些或所有分区的访问。 连接到控制器的主机发出命令，并且控制器根据命令的性质以各种方式分析命令并对其进行响应。 特别地，根据命令的性质，控制器可以将命令传递到智能卡设备，或者无限期地忽略该命令，或直到发生预定事件。
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公开(公告)号：US07102671B1
公开(公告)日：2006-09-05
申请号：US09500755
申请日：2000-02-08
申请人： Mehdi Asnaashari
发明人： Mehdi Asnaashari
IPC分类号： H04N5/76
CPC分类号： H04N1/00204 , G06F3/0601 , G06F2003/0692 , H04N1/2158 , H04N2201/0051 , H04N2201/0062 , H04N2201/0084
摘要： An embodiment of the present invention includes a digital camera system having a digital camera and a computer for transferring pictures of images taken by the digital camera therebetween. The digital camera system includes a card removably and directly coupled, without any intermediary device, between the digital camera and the computer for temporarily storing the images and for transferring the temporarily stored images to the computer for viewing, editing and reproduction thereof.
摘要翻译： 本发明的实施例包括具有数字照相机和计算机的数字照相机系统，用于传送由数字照相机拍摄的图像的照片。 数字照相机系统包括在数字照相机和计算机之间可拆卸地和直接地耦合在数字照相机和计算机之间的卡，用于暂时存储图像并将临时存储的图像传送到计算机以供其观看，编辑和再现。
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公开(公告)号：US5564055A
公开(公告)日：1996-10-08
申请号：US298240
申请日：1994-08-30
申请人： Mehdi Asnaashari , Duc N. Pham
发明人： Mehdi Asnaashari , Duc N. Pham
CPC分类号： G06F12/0615
摘要： A PCMCIA slot expander provides a fully functional PCMCIA slot having a 32 MB address space and at least one other resource to a computer or other device having at least one PCMCIA slot. In an illustrated embodiment, a PCMCIA slot is expanded to provide a fully functional PCMCIA slot having a 32 MB address space, an embedded substantially functional PCMCIA slot, first and second serial ports, a parallel port and diagnostic information and access to signals carried on the PCMCIA slot.
摘要翻译： PCMCIA插槽扩展器为具有至少一个PCMCIA插槽的计算机或其他设备提供具有32MB地址空间的全功能PCMCIA插槽和至少一个其他资源。 在所示实施例中，扩展PCMCIA时隙以提供具有32MB地址空间的完全功能的PCMCIA时隙，嵌入式基本功能的PCMCIA时隙，第一和第二串行端口，并行端口和诊断信息以及对 PCMCIA插槽。
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公开(公告)号：US08966231B2
公开(公告)日：2015-02-24
申请号：US13270675
申请日：2011-10-11
申请人： Mehdi Asnaashari
发明人： Mehdi Asnaashari
CPC分类号： G06F13/1642 , G06F13/1631
摘要： The present disclosure includes methods, devices, modules, and systems for modifying commands. One device embodiment includes a memory controller including a channel, wherein the channel includes a command queue configured to hold commands, and circuitry configured to modify at least a number of commands in the queue and execute the modified commands.
摘要翻译： 本公开包括用于修改命令的方法，设备，模块和系统。 一个设备实施例包括包括信道的存储器控制器，其中信道包括被配置为保存命令的命令队列，以及被配置为修改队列中的至少多个命令并执行修改的命令的电路。
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公开(公告)号：US08887270B2
公开(公告)日：2014-11-11
申请号：US11938681
申请日：2007-11-12
申请人： Mehdi Asnaashari , Victor Tsai
发明人： Mehdi Asnaashari , Victor Tsai
CPC分类号： G06F12/1408 , G06F21/602 , G06F21/77 , G06F21/79 , G06F2212/1052 , H04L9/0897 , H04L9/3226
摘要： A smart storage device can have a smart-card portion with access control circuitry and integrated memory, a controller in selective communication with the smart-card portion, and a memory device in communication with the controller. The memory device can be separate from the smart-card portion and can store one or more smart-card applications.
摘要翻译： 智能存储设备可以具有带有访问控制电路和集成存储器的智能卡部分，与智能卡部分选择性通信的控制器以及与控制器通信的存储器设备。 存储设备可以与智能卡部分分开并且可以存储一个或多个智能卡应用。
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