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66 条记录 (耗时 0.028 秒)

    Integration scheme for enhancing capacitance of trench capacitors
    41.
    发明授权
    Integration scheme for enhancing capacitance of trench capacitors 失效
    用于增强沟槽电容器电容的集成方案

    公开(公告)号：US06806138B1

    公开(公告)日：2004-10-19

    申请号：US10707890

    申请日：2004-01-21

    申请人： Kangguo Cheng ,  Hiroyuki Akatsu ,  Rama Divakaruni

    发明人： Kangguo Cheng ,  Hiroyuki Akatsu ,  Rama Divakaruni

    IPC分类号： H01L218242

    CPC分类号： H01L27/1087 ,  H01L29/66181 ,  H01L29/945

    摘要： The capacitance of deep trench capacitors is enhanced by increasing the surface area of the doped region of the trench to be used for one electrode of the capacitor. After formation of the deep trench and a collar on an upper region of the trench, and after optional bottling of the trench, hemispherical silicon grain (HSG) is deposited on a lower region of the trench. The HSG is then oxidized, along with that portion of the silicon substrate not covered by HSG, to form a roughened surface in the trench, thereby enhancing the trench capacitance. Oxidation of the HSG and the substrate occurs simultaneously with formation of the buried plate, and the formed oxide may be stripped along with the collar, thereby providing a simpler and more robust capacitance enhancement scheme.

    摘要翻译： 通过增加用于电容器的一个电极的沟槽的掺杂区域的表面积来增强深沟槽电容器的电容。 在沟槽的上部区域形成深沟槽和套环之后，在沟槽的可选装填之后，半沟球硅晶粒（HSG）沉积在沟槽的下部区域上。 然后HSG与不被HSG覆盖的硅衬底的那部分一起氧化，以在沟槽中形成粗糙化表面，从而增强沟槽电容。 HSG和衬底的氧化与掩埋板的形成同时发生，并且所形成的氧化物可以与套环一起剥离，从而提供更简单和更坚固的电容增强方案。

    PMOSFET device with localized nitrogen sidewall implantation
    42.
    发明授权
    PMOSFET device with localized nitrogen sidewall implantation 有权
    具有局部氮侧壁注入的PMOSFET器件

    公开(公告)号：US06724053B1

    公开(公告)日：2004-04-20

    申请号：US09511395

    申请日：2000-02-23

    申请人： Rama Divakaruni ,  Ryota Katsumata ,  Giuseppe La Rosa ,  Rajesh Rengarajan ,  Mary E. Weybright

    发明人： Rama Divakaruni ,  Ryota Katsumata ,  Giuseppe La Rosa ,  Rajesh Rengarajan ,  Mary E. Weybright

    IPC分类号： H01L2976

    CPC分类号： H01L21/823878 ,  H01L21/26506 ,  H01L21/2658 ,  H01L21/28123 ,  H01L21/823481 ,  H01L29/1033 ,  H01L29/1041 ,  H01L29/7838

    摘要： P-type metal-oxide semiconductor field effect transistor (PMOSFET) devices have a characteristic property known as threshold voltage. This threshold voltage may consist of separate threshold voltages associated with the main portion of the gate region of the device and with the sidewall corner of the device. Under some conditions, the threshold behavior in the sidewall corner region of the device may dominate the performance of the device, not necessarily in the manner intended by the designer of the device. A method of controlling threshold voltage behavior is described. In particular, ion implantation of nitrogen in the gate sidewall region of the device can provide such control. Devices made by this method are also described.

    摘要翻译： P型金属氧化物半导体场效应晶体管（PMOSFET）器件具有被称为阈值电压的特性。 该阈值电压可以由与器件的栅极区域的主要部分和器件的侧壁角相关联的单独的阈值电压组成。 在某些情况下，设备的侧壁角区域中的阈值行为可能主导设备的性能，而不一定是设备设计者所期望的方式。 描述了一种控制阈值电压特性的方法。 特别地，器件的栅极侧壁区域中的氮的离子注入可以提供这种控制。 还描述了通过该方法制造的装置。

    Structure and method for dual work function logic devices in vertical DRAM process
    43.
    发明授权
    Structure and method for dual work function logic devices in vertical DRAM process 有权
    垂直DRAM过程中双功能逻辑器件的结构和方法

    公开(公告)号：US06635526B1

    公开(公告)日：2003-10-21

    申请号：US10165171

    申请日：2002-06-07

    申请人： Rajeev Malik ,  Rama Divakaruni ,  Rajesh Rengarajan

    发明人： Rajeev Malik ,  Rama Divakaruni ,  Rajesh Rengarajan

    IPC分类号： H01L218242

    CPC分类号： H01L27/10864 ,  H01L27/10841 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/66181 ,  H01L29/945

    摘要： Dual work function transistors are provided in a cmos support area 14 with an embedded vertical dram array 12. A wordline layer 54, and nitride cap layer 56 cover the dram array 12 and a gate oxide layer 42 and an undoped polysilicon layer 44 cover the support area 14. A common mask is applied and patterned over the substrate to define the wordlines line structures in the dram array 12 and the gate structures in the support 14. The unwanted portions of the layers 54, 56, 42 and 44 are removed by etching.

    摘要翻译： 双工作功能晶体管被设置在具有嵌入式垂直电极阵列12的cmos支撑区域14中。字线层54和氮化物覆盖层56覆盖电弧阵列12，栅极氧化物层42和未掺杂的多晶硅层44覆盖支撑体 在衬底上施加和图案化通用掩模，以限定电极阵列12中的字线线结构和支撑件14中的栅极结构。通过蚀刻去除层54,56,42和44的不需要的部分 。

    Structure and process for fabricating a 6F2 DRAM cell having vertical MOSFET and large trench capacitance
    45.
    发明授权
    Structure and process for fabricating a 6F2 DRAM cell having vertical MOSFET and large trench capacitance 失效
    用于制造具有垂直MOSFET和大沟槽电容的6F2 DRAM单元的结构和工艺

    公开(公告)号：US06288422B1

    公开(公告)日：2001-09-11

    申请号：US09540276

    申请日：2000-03-31

    申请人： Jack A. Mandelman ,  Rama Divakaruni ,  Carl Radens

    发明人： Jack A. Mandelman ,  Rama Divakaruni ,  Carl Radens

    IPC分类号： H01L27108

    CPC分类号： H01L27/10864 ,  H01L27/10867 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/945

    摘要： A 6F2 memory cell structure comprising a plurality of capacitors each located in a separate trench in a substrate; a pluralaity of transfer transistors each having a vertical gate dielectric, a gate conductor, and a bitline diffusion, each transistor being located above and electrically connected to a respective trench capacitor; a plurality of troughs in a striped pattern about said transistor, said troughs being spaced apart by a substantially uniform spacing, said plurality of striped troughs comprising a first group of troughs consisting of every other one of said troughs being filled with a dielectric material, and a second group of troughs being the remaining troughs of said plurality, said second group of troughs containing dielectric material, damascened wordlines and damascene wordline contacts; a respective wordline electrical contact connected to each respective gate conductor; and a bitline contacted to each bitline diffusion, wherein said bitline diffusions have a width defined by said spacing of said striped troughs and each wordline electrical contact is self-aligned to an edge of a trough of said second group of troughs.

    摘要翻译： 6F2存储器单元结构，包括多个电容器，每个电容器位于衬底中的单独的沟槽中; 每个具有垂直栅极电介质，栅极导体和位线扩散的转移晶体管的多个，每个晶体管位于相应的沟槽电容器的上方并电连接到相应的沟槽电容器; 围绕所述晶体管的条纹图案的多个槽，所述槽以基本上均匀的间隔间隔开，所述多个条纹槽包括由每一个所述槽中的每一个填充有电介质材料构成的第一组槽，以及 第二组槽是所述多个的剩余槽，所述第二组槽包含电介质材料，大阴影字线和大马士革字线触点; 连接到每个相应的栅极导体的相应字线电触头; 并且与每个位线扩散接触的位线，其中所述位线扩散具有由所述条纹槽的所述间隔限定的宽度，并且每个字线电触点与所述第二组槽的槽的边缘自对准。

    Method for dual sidewall oxidation in high density, high performance DRAMS
    46.
    发明授权
    Method for dual sidewall oxidation in high density, high performance DRAMS 失效
    高密度，高性能DRAMS双壁氧化方法

    公开(公告)号：US06197632B1

    公开(公告)日：2001-03-06

    申请号：US09440776

    申请日：1999-11-16

    申请人： Gary B. Bronner ,  Rama Divakaruni ,  Scott Halle ,  Dale W. Martin ,  Rajesh Rengarajan ,  Mary E. Weybright

    发明人： Gary B. Bronner ,  Rama Divakaruni ,  Scott Halle ,  Dale W. Martin ,  Rajesh Rengarajan ,  Mary E. Weybright

    IPC分类号： H01L218242

    CPC分类号： H01L27/10894 ,  H01L27/10873 ,  H01L29/6659

    摘要： This invention relates to integrated circuit product and processes. More particularly, the invention relates to high performance Dynamic Random Access Memory (DRAM) chips and processes for making such chips. An IC fabrication is provided, according to an aspect of the invention, including a silicon wafer, a DRAM array fabrication disposed on said silicon wafer having a first multitude of gate sidewall oxides, and a logic support device fabrication disposed on said wafer adjacent said DRAM array fabrication and having a second multitude of gate sidewall oxides, said first multitude of gate sidewall oxides being substantially thicker than said second multitude of gate sidewall oxides. Methods of making IC fabrications according to the invention are also provided.

    摘要翻译： 本发明涉及集成电路产品和工艺。 更具体地，本发明涉及高性能动态随机存取存储器（DRAM）芯片和用于制造这种芯片的过程。 提供根据本发明的一个方面的IC制造，包括硅晶片，设置在具有第一多个栅极侧壁氧化物的所述硅晶片上的DRAM阵列制造，以及设置在与所述DRAM相邻的所述晶片上的逻辑支持器件制造 阵列制造并具有第二多个栅极侧壁氧化物，所述第一多个栅极侧壁氧化物基本上比所述第二多个栅极侧壁氧化物厚。 还提供了制造根据本发明的IC制造的方法。

    Method of fabricating self-aligned bipolar transistor having tapered collector
    48.
    发明申请
    Method of fabricating self-aligned bipolar transistor having tapered collector 有权
    制造具有锥形集电极的自对准双极晶体管的方法

    公开(公告)号：US20080318373A1

    公开(公告)日：2008-12-25

    申请号：US12220521

    申请日：2008-07-25

    申请人： Hiroyuki Akatsu ,  Rama Divakaruni ,  Gregory G. Freeman ,  David R. Greenberg ,  Marwan H. Khater ,  William R. Tonti

    发明人： Hiroyuki Akatsu ,  Rama Divakaruni ,  Gregory G. Freeman ,  David R. Greenberg ,  Marwan H. Khater ,  William R. Tonti

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/66242 ,  H01L29/0821 ,  H01L29/7378

    摘要： A method is provided for making a bipolar transistor which includes a tapered, i.e. frustum-shaped, collector pedestal having an upper substantially planar surface, a lower surface, and a slanted sidewall extending between the upper surface and the lower surface, the upper surface having substantially less area than the lower surface. The collector pedestal can be formed on a surface of a collector active region exposed within an opening extending through first and second overlying dielectric regions, where the opening defines vertically aligned edges of the first and second dielectric regions.

    摘要翻译： 提供了一种用于制造双极晶体管的方法，该双极晶体管包括锥形的，即截头锥形的收集器基座，其具有上部基本平坦的表面，下表面和在上表面和下表面之间延伸的倾斜侧壁，上表面具有 比下表面小得多的面积。 收集器基座可以形成在暴露在通过第一和第二覆盖介质区域延伸的开口内的集电极有源区域的表面上，其中开口限定第一和第二电介质区域的垂直对齐的边缘。

    Method of fabricating a bipolar transistor having reduced collector-base capacitance
    49.
    发明授权
    Method of fabricating a bipolar transistor having reduced collector-base capacitance 失效
    制造具有减小的集电极 - 基极电容的双极晶体管的方法

    公开(公告)号：US07462547B2

    公开(公告)日：2008-12-09

    申请号：US11633380

    申请日：2006-12-04

    申请人： Hiroyuki Akatsu ,  Rama Divakaruni ,  Marwan Khater ,  Christopher M. Schnabel ,  William Tonti

    发明人： Hiroyuki Akatsu ,  Rama Divakaruni ,  Marwan Khater ,  Christopher M. Schnabel ,  William Tonti

    IPC分类号： H01L21/331 ,  H01L27/082

    CPC分类号： H01L29/66242 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0821

    摘要： A method is provided for fabricating a bipolar transistor that includes growing an epitaxial layer onto an underlaying region having a low dopant concentration and a trench isolation region defining the edges of an active region layer, implanting a portion of the epitaxial layer through a mask to define a collector region having a relatively high dopant concentration, the collector region laterally adjoining a second region of the epitaxial layer having the low dopant concentration; forming an intrinsic base layer overlying the collector region and the second region, the intrinsic base layer including an epitaxial region in conductive communication with the collector region; forming a low-capacitance region laterally separated from the collector region by the second region, the low-capacitance region including a dielectric region disposed in an undercut directly underlying the intrinsic base layer; and forming an emitter layer overlying the intrinsic base layer.

    摘要翻译： 提供了一种用于制造双极晶体管的方法，该双极晶体管包括将外延层生长到具有低掺杂剂浓度的衬底区域和限定有源区域层的边缘的沟槽隔离区域，通过掩模注入外延层的一部分以限定 具有相对较高掺杂剂浓度的集电极区域，所述集电极区域横向邻接所述外延层的具有低掺杂浓度的第二区域; 形成覆盖所述集电极区域和所述第二区域的本征基极层，所述本征基极层包括与所述集电极区域导通连通的外延区域; 形成由所述第二区域与所述集电极区域横向分离的低电容区域，所述低电容区域包括设置在所述本征基极层下方的底切处的电介质区域; 并形成覆盖本征基层的发射极层。