利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

66 条记录 (耗时 0.031 秒)

    Structure and method of self-aligned bipolar transistor having tapered collector
    1.
    发明授权
    Structure and method of self-aligned bipolar transistor having tapered collector 有权
    具有锥形集电极的自对准双极晶体管的结构和方法

    公开(公告)号：US07425754B2

    公开(公告)日：2008-09-16

    申请号：US10708340

    申请日：2004-02-25

    申请人： Hiroyuki Akatsu ,  Rama Divakaruni ,  Gregory G. Freeman ,  David R. Greenberg ,  Marwan H. Khater ,  William R. Tonti

    发明人： Hiroyuki Akatsu ,  Rama Divakaruni ,  Gregory G. Freeman ,  David R. Greenberg ,  Marwan H. Khater ,  William R. Tonti

    IPC分类号： H01L27/102

    CPC分类号： H01L29/66242 ,  H01L29/0821 ,  H01L29/7378

    摘要： A bipolar transistor is provided which includes a tapered, i.e. frustum-shaped, collector pedestal having an upper substantially planar surface, a lower surface, and a slanted sidewall extending between the upper surface and the lower surface, the upper surface having substantially less area than the lower surface. The bipolar transistor further includes an intrinsic base overlying the upper surface of the collector pedestal, a raised extrinsic base conductively connected to the intrinsic base and an emitter overlying the intrinsic base. In a particular embodiment, the emitter is self-aligned to the collector pedestal, having a centerline which is aligned to the centerline of the collector pedestal.

    摘要翻译： 提供了一种双极晶体管，其包括锥形的，即截头锥形的收集器基座，其具有上部基本平坦的表面，下表面和在上表面和下表面之间延伸的倾斜侧壁，上表面具有基本上较小的面积 下表面。 双极晶体管还包括覆盖集电极基座的上表面的本征基极，与本征基极导电连接的升高的外部基极和覆盖本征基极的发射极。 在特定实施例中，发射器与收集器基座自对准，具有与收集器基座的中心线对准的中心线。

    Method of fabricating self-aligned bipolar transistor having tapered collector
    3.
    发明申请
    Method of fabricating self-aligned bipolar transistor having tapered collector 有权
    制造具有锥形集电极的自对准双极晶体管的方法

    公开(公告)号：US20080318373A1

    公开(公告)日：2008-12-25

    申请号：US12220521

    申请日：2008-07-25

    申请人： Hiroyuki Akatsu ,  Rama Divakaruni ,  Gregory G. Freeman ,  David R. Greenberg ,  Marwan H. Khater ,  William R. Tonti

    发明人： Hiroyuki Akatsu ,  Rama Divakaruni ,  Gregory G. Freeman ,  David R. Greenberg ,  Marwan H. Khater ,  William R. Tonti

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/66242 ,  H01L29/0821 ,  H01L29/7378

    摘要： A method is provided for making a bipolar transistor which includes a tapered, i.e. frustum-shaped, collector pedestal having an upper substantially planar surface, a lower surface, and a slanted sidewall extending between the upper surface and the lower surface, the upper surface having substantially less area than the lower surface. The collector pedestal can be formed on a surface of a collector active region exposed within an opening extending through first and second overlying dielectric regions, where the opening defines vertically aligned edges of the first and second dielectric regions.

    摘要翻译： 提供了一种用于制造双极晶体管的方法，该双极晶体管包括锥形的，即截头锥形的收集器基座，其具有上部基本平坦的表面，下表面和在上表面和下表面之间延伸的倾斜侧壁，上表面具有 比下表面小得多的面积。 收集器基座可以形成在暴露在通过第一和第二覆盖介质区域延伸的开口内的集电极有源区域的表面上，其中开口限定第一和第二电介质区域的垂直对齐的边缘。

    Shared body and diffusion contact structure and method for fabricating same
    4.
    发明授权
    Shared body and diffusion contact structure and method for fabricating same 失效
    共享体和扩散接触结构及其制造方法

    公开(公告)号：US06429477B1

    公开(公告)日：2002-08-06

    申请号：US09702315

    申请日：2000-10-31

    申请人： Jack A. Mandelman ,  Rama Divakaruni ,  William R. Tonti

    发明人： Jack A. Mandelman ,  Rama Divakaruni ,  William R. Tonti

    IPC分类号： H01L2976

    CPC分类号： H01L27/10861 ,  H01L21/743 ,  H01L21/76897 ,  H01L27/0214 ,  H01L27/10888 ,  H01L27/1203

    摘要： The preferred embodiment overcomes the difficulties found in the background art by providing a body contact and diffusion contact formed in a single shared via for silicon on insulator (SOI) technologies. By forming the body contact and diffusion contact in a single shared via, device size is minimized and performance is improved. Particularly, the formed body contact connects the SOI layer with the underlying substrate to avoid instabilities and leakage resulting from a floating SOI channel region. The formed diffusion contact connects device diffusions to above wiring to facilitate device operation. By providing the body contact and diffusion contact together in a single shared via, the preferred embodiment avoids the area penalty that would result from separate contacts. Additionally, the preferred embodiment provides a body contact that is self aligned with other devices, minimizing tolerances needed while minimizing process complexity. Additionally, the shared via body contact and diffusion contact can be selectively formed borderless to adjacent gate conductors in the device.

    摘要翻译： 优选实施例通过提供在用于绝缘体上硅（SOI）技术的单个共享通孔中形成的体接触和扩散接触来克服背景技术中发现的困难。 通过在单个共享通孔中形成体接触和扩散接触，器件尺寸最小化并且性能得到改善。 特别地，形成的体接触将SOI层与底层衬底连接，以避免由浮动SOI沟道区产生的不稳定性和漏电。 形成的扩散触点将器件扩散连接到上述布线以便于器件操作。 通过在单个共享通孔中将身体接触和扩散接触提供在一起，优选的实施例避免了由单独接触引起的区域损失。 此外，优选实施例提供与其他装置自对准的身体接触，使尽可能少的过程复杂性所需的公差最小化。 此外，共享的通孔体接触和扩散接触可以选择性地形成与设备中的相邻栅极导体无边界。

    STRUCTURE AND METHOD OF SELF-ALIGNED BIPOLAR TRANSISTOR HAVING TAPERED COLLECTOR
    5.
    发明申请
    STRUCTURE AND METHOD OF SELF-ALIGNED BIPOLAR TRANSISTOR HAVING TAPERED COLLECTOR 有权
    带有收集器的自对准双极晶体管的结构和方法

    公开(公告)号：US20050184359A1

    公开(公告)日：2005-08-25

    申请号：US10708340

    申请日：2004-02-25

    申请人： Hiroyuki Akatsu ,  Rama Divakaruni ,  Gregory Freeman ,  David Greenberg ,  Marwan Khater ,  William Tonti

    发明人： Hiroyuki Akatsu ,  Rama Divakaruni ,  Gregory Freeman ,  David Greenberg ,  Marwan Khater ,  William Tonti

    IPC分类号： H01L21/331 ,  H01L27/082 ,  H01L29/08 ,  H01L29/737

    CPC分类号： H01L29/66242 ,  H01L29/0821 ,  H01L29/7378

    摘要： A bipolar transistor is provided which includes a tapered, i.e. frustum-shaped, collector pedestal having an upper substantially planar surface, a lower surface, and a slanted sidewall extending between the upper surface and the lower surface, the upper surface having substantially less area than the lower surface. The bipolar transistor further includes an intrinsic base overlying the upper surface of the collector pedestal, a raised extrinsic base conductively connected to the intrinsic base and an emitter overlying the intrinsic base. In a particular embodiment, the emitter is self-aligned to the collector pedestal, having a centerline which is aligned to the centerline of the collector pedestal.

    摘要翻译： 提供了一种双极晶体管，其包括锥形的，即截头锥形的收集器基座，其具有上部基本平坦的表面，下表面和在上表面和下表面之间延伸的倾斜侧壁，上表面具有基本上较小的面积 下表面。 双极晶体管还包括覆盖集电极基座的上表面的本征基极，与本征基极导电连接的升高的外部基极和覆盖本征基极的发射极。 在特定实施例中，发射器与收集器基座自对准，具有与收集器基座的中心线对准的中心线。

    Fabrication of bipolar transistor having reduced collector-base capacitance
    8.
    发明申请
    Fabrication of bipolar transistor having reduced collector-base capacitance 失效
    具有减小的集电极 - 基极电容的双极晶体管的制造

    公开(公告)号：US20070096259A1

    公开(公告)日：2007-05-03

    申请号：US11633380

    申请日：2006-12-04

    申请人： Hiroyuki Akatsu ,  Rama Divakaruni ,  Marwan Khater ,  Christopher Schnabel ,  William Tonti

    发明人： Hiroyuki Akatsu ,  Rama Divakaruni ,  Marwan Khater ,  Christopher Schnabel ,  William Tonti

    IPC分类号： H01L27/082

    CPC分类号： H01L29/66242 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0821

    摘要： A method is provided for fabricating a bipolar transistor in which a collector layer is formed which includes an active portion having a relatively high dopant concentration and a second portion which has a lower dopant concentration. An epitaxial intrinsic base layer is formed to overlie the collector layer in conductive communication with the active portion of the collector layer. A low-capacitance region is formed laterally adjacent to the second portion of the collector layer, the low-capacitance region including a dielectric region disposed in an undercut directly underlying the intrinsic base layer. An emitter layer is formed to overlie the intrinsic base layer.

    摘要翻译： 提供一种用于制造双极晶体管的方法，其中形成集电极层，其包括具有较高掺杂剂浓度的有源部分和具有较低掺杂剂浓度的第二部分。 外延本征基极层形成为覆盖集电极层，与集电极层的有源部分导电连通。 低电容区域形成为与集电极层的第二部分横向相邻，低电容区域包括设置在直接位于本征基极层下方的底切处的电介质区域。 形成发射极层以覆盖本征基极层。

    Integration scheme for enhancing capacitance of trench capacitors
    9.
    发明授权
    Integration scheme for enhancing capacitance of trench capacitors 失效
    用于增强沟槽电容器电容的集成方案

    公开(公告)号：US06806138B1

    公开(公告)日：2004-10-19

    申请号：US10707890

    申请日：2004-01-21

    申请人： Kangguo Cheng ,  Hiroyuki Akatsu ,  Rama Divakaruni

    发明人： Kangguo Cheng ,  Hiroyuki Akatsu ,  Rama Divakaruni

    IPC分类号： H01L218242

    CPC分类号： H01L27/1087 ,  H01L29/66181 ,  H01L29/945

    摘要： The capacitance of deep trench capacitors is enhanced by increasing the surface area of the doped region of the trench to be used for one electrode of the capacitor. After formation of the deep trench and a collar on an upper region of the trench, and after optional bottling of the trench, hemispherical silicon grain (HSG) is deposited on a lower region of the trench. The HSG is then oxidized, along with that portion of the silicon substrate not covered by HSG, to form a roughened surface in the trench, thereby enhancing the trench capacitance. Oxidation of the HSG and the substrate occurs simultaneously with formation of the buried plate, and the formed oxide may be stripped along with the collar, thereby providing a simpler and more robust capacitance enhancement scheme.

    摘要翻译： 通过增加用于电容器的一个电极的沟槽的掺杂区域的表面积来增强深沟槽电容器的电容。 在沟槽的上部区域形成深沟槽和套环之后，在沟槽的可选装填之后，半沟球硅晶粒（HSG）沉积在沟槽的下部区域上。 然后HSG与不被HSG覆盖的硅衬底的那部分一起氧化，以在沟槽中形成粗糙化表面，从而增强沟槽电容。 HSG和衬底的氧化与掩埋板的形成同时发生，并且所形成的氧化物可以与套环一起剥离，从而提供更简单和更坚固的电容增强方案。

    Method of fabricating a bipolar transistor having reduced collector-base capacitance
    10.
    发明授权
    Method of fabricating a bipolar transistor having reduced collector-base capacitance 失效
    制造具有减小的集电极 - 基极电容的双极晶体管的方法

    公开(公告)号：US07462547B2

    公开(公告)日：2008-12-09

    申请号：US11633380

    申请日：2006-12-04

    申请人： Hiroyuki Akatsu ,  Rama Divakaruni ,  Marwan Khater ,  Christopher M. Schnabel ,  William Tonti

    发明人： Hiroyuki Akatsu ,  Rama Divakaruni ,  Marwan Khater ,  Christopher M. Schnabel ,  William Tonti

    IPC分类号： H01L21/331 ,  H01L27/082

    CPC分类号： H01L29/66242 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0821

    摘要： A method is provided for fabricating a bipolar transistor that includes growing an epitaxial layer onto an underlaying region having a low dopant concentration and a trench isolation region defining the edges of an active region layer, implanting a portion of the epitaxial layer through a mask to define a collector region having a relatively high dopant concentration, the collector region laterally adjoining a second region of the epitaxial layer having the low dopant concentration; forming an intrinsic base layer overlying the collector region and the second region, the intrinsic base layer including an epitaxial region in conductive communication with the collector region; forming a low-capacitance region laterally separated from the collector region by the second region, the low-capacitance region including a dielectric region disposed in an undercut directly underlying the intrinsic base layer; and forming an emitter layer overlying the intrinsic base layer.

    摘要翻译： 提供了一种用于制造双极晶体管的方法，该双极晶体管包括将外延层生长到具有低掺杂剂浓度的衬底区域和限定有源区域层的边缘的沟槽隔离区域，通过掩模注入外延层的一部分以限定 具有相对较高掺杂剂浓度的集电极区域，所述集电极区域横向邻接所述外延层的具有低掺杂浓度的第二区域; 形成覆盖所述集电极区域和所述第二区域的本征基极层，所述本征基极层包括与所述集电极区域导通连通的外延区域; 形成由所述第二区域与所述集电极区域横向分离的低电容区域，所述低电容区域包括设置在所述本征基极层下方的底切处的电介质区域; 并形成覆盖本征基层的发射极层。