公开(公告)号：US20100200934A1

公开(公告)日：2010-08-12

申请号：US12702682

申请日：2010-02-09

申请人： Xiangdong Chen ,  Brian J. Greene ,  Haining S. Yang

发明人： Xiangdong Chen ,  Brian J. Greene ,  Haining S. Yang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/28194 ,  H01L29/1054 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66651

摘要： A field effect structure and a method for fabricating the field effect structure include a germanium containing channel interposed between a plurality of source and drain regions. The germanium containing channel is coplanar with the plurality of source and drain regions, and the germanium containing channel includes a germanium containing material having a germanium content greater than the germanium content of the plurality of source and drain regions.

摘要翻译： 场效应结构和用于制造场效应结构的方法包括介于多个源区和漏区之间的含锗通道。 含锗通道与多个源极和漏极区域共面，并且含锗沟道包括锗含量大于多个源极和漏极区的锗含量的含锗材料。

公开(公告)号：US20080251853A1

公开(公告)日：2008-10-16

申请号：US12144800

申请日：2008-06-24

申请人： Xiangdong Chen ,  Haining S. Yang

发明人： Xiangdong Chen ,  Haining S. Yang

IPC分类号： H01L27/092

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823842 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure of strained MOSFETs, comprising both PMOSFETs and NMOSFETS, and a method for fabricating strained MOSFETs are disclosed that optimize strain in the MOSFETs, and more particularly maximize the strain in one kind (P or N) of MOSFET and minimize and relax the strain in another kind (N or P) of MOSFET. A strain inducing CA nitride coating having an original full thickness is formed over both the PMOSFETs and the NMOSFETs, wherein the strain inducing coating produces an optimized full strain in one kind of semiconductor device and degrades the performance of the other kind of semiconductor device. The strain inducing CA nitride coating is etched to a reduced thickness over the other kind of semiconductor devices, wherein the reduced thickness of the strain inducing coating relaxes and produces less strain in the other MOSFETs.

公开(公告)号：US20080191788A1

公开(公告)日：2008-08-14

申请号：US11672592

申请日：2007-02-08

申请人： Xiangdong Chen ,  Haining S. Yang

发明人： Xiangdong Chen ,  Haining S. Yang

IPC分类号： G05F1/10 ,  H01L21/336

CPC分类号： H01L29/66772 ,  H01L29/78609

摘要： An SOI semiconductor device includes a silicon semiconductor layer divided into an FET region with source, channel, and drain regions therein formed on a BOX layer, with a switch region next to the FET region; and a contact region next to the switch region distal from the FET region. The FET region has a greater thickness than the switch region. A conformal gate dielectric layer covers the FET region and the switch. A dual function gate electrode formed over the gate dielectric layer includes an FET portion above the FET region and an auxiliary gate portion extending therefrom above the switch region. A contact is formed reaching through the gate dielectric layer into electrical and mechanical contact with the contact region. The switch varies the depth of the depletion region to open and close current flow between the channel of the FET device and the contact region to suppress subthreshold leakage current.

摘要翻译： SOI半导体器件包括分成FET区域的硅半导体层，其中源区，沟道和漏极区域形成在BOX层上，开关区域紧邻FET区域; 以及在远离FET区域的开关区域旁边的接触区域。 FET区域具有比开关区域更大的厚度。 保形栅极电介质层覆盖FET区域和开关。 形成在栅极电介质层上的双功能栅极电极包括FET区域上方的FET部分和从开关区域上方延伸的辅助栅极部分。 形成通过栅介质层到达接触区域的电接触和机械接触的接触。 该开关改变耗尽区的深度以打开和关闭FET器件的沟道与接触区之间的电流，以抑制亚阈值漏电流。

公开(公告)号：US20080087965A1

公开(公告)日：2008-04-17

申请号：US11548296

申请日：2006-10-11

申请人： Xiangdong Chen ,  Haining S. Yang

发明人： Xiangdong Chen ,  Haining S. Yang

IPC分类号： H01L21/31 ,  H01L29/78

CPC分类号： H01L29/7843 ,  H01L21/3185 ,  H01L21/823412 ,  H01L27/088 ,  H01L29/665 ,  H01L29/78

摘要： A method for increasing carrier mobility of transistors included in an semiconductor device includes forming a stress inducing layer over a plurality of transistors, the transistors formed in regions of varying transistor density, wherein the stress inducing layer is formed at a varying thickness depending on the transistor density, such that the stress inducing layer is thicker in regions of increased transistor density and thinner in regions of decreased transistor density.

摘要翻译： 一种用于增加包括在半导体器件中的晶体管的载流子迁移率的方法包括在多个晶体管上形成应力感应层，所述晶体管形成在具有变化的晶体管密度的区域中，其中应力诱导层根据晶体管形成为变化的厚度 使得应力诱导层在晶体管密度增加的区域较厚，晶体管密度降低的区域较薄。

公开(公告)号：US08441000B2

公开(公告)日：2013-05-14

申请号：US11307331

申请日：2006-02-01

申请人： Xiangdong Chen ,  Haining S. Yang

发明人： Xiangdong Chen ,  Haining S. Yang

IPC分类号： H01L29/06

CPC分类号： H01L29/78 ,  H01L29/165 ,  H01L29/66356 ,  H01L29/7391

摘要： The present invention relates to a heterojunction tunneling effect transistor (TFET), which comprises spaced apart source and drain regions with a channel region located therebetween and a gate stack located over the channel region. The drain region comprises a first semiconductor material and is doped with a first dopant species of a first conductivity type. The source region comprises a second, different semiconductor material and is doped with a second dopant species of a second, different conductivity type. The gate stack comprises at least a gate dielectric and a gate conductor. When the heterojunction TFET is an n-channel TFET, the drain region comprises n-doped silicon, while the source region comprises p-doped silicon germanium. When the heterojunction TFET is a p-channel TPET, the drain region comprises p-doped silicon, while the source region comprises n-doped SiC.

摘要翻译： 本发明涉及异质结隧道效应晶体管（TFET），其包括间隔开的源极和漏极区，其中位于其间的沟道区和位于沟道区上方的栅极叠层。 漏极区域包括第一半导体材料并且掺杂有第一导电类型的第一掺杂物种类。 源区包括第二不同的半导体材料，并且掺杂有第二不同导电类型的第二掺杂物种。 栅极堆叠至少包括栅极电介质和栅极导体。 当异质结TFET是n沟道TFET时，漏极区域包括n掺杂的硅，而源极区域包括p掺杂的硅锗。 当异质结TFET是p沟道TPET时，漏极区包括p掺杂的硅，而源区包括n掺杂的SiC。

公开(公告)号：US07741217B2

公开(公告)日：2010-06-22

申请号：US11924045

申请日：2007-10-25

申请人： Haining S. Yang ,  Xiangdong Chen

发明人： Haining S. Yang ,  Xiangdong Chen

IPC分类号： H01L21/8238

CPC分类号： H01L29/7391 ,  H01L27/0629 ,  H01L27/0811 ,  H01L27/0814 ,  H01L29/402 ,  H01L29/456 ,  H01L29/66356 ,  H01L29/861

摘要： A CMOS diode and method of making it are disclosed. In one embodiment, the diode comprises a silicon substrate having an N doped region and a P doped region. A first silicide region is formed on the N doped region of the silicon substrate, and a second silicide region formed on the P doped region of the silicon substrate. The first silicide region is comprised of a material having a bandgap value lower than the bandgap value of the material comprising the second silicide region. The result is a diode where the workfunction of each region of silicide more closely matches the workfunction of the doped silicon it contacts, resulting in reduced contact resistance. This provides for a diode with improved performance characteristics.

摘要翻译： 公开了一种CMOS二极管及其制造方法。 在一个实施例中，二极管包括具有N掺杂区域和P掺杂区域的硅衬底。 在硅衬底的N掺杂区域上形成第一硅化物区域，以及形成在硅衬底的P掺杂区域上的第二硅化物区域。 第一硅化物区域由具有低于包含第二硅化物区域的材料的带隙值的带隙值的材料构成。 结果是二极管，其中硅化物的每个区域的功函数与其接触的掺杂硅的功函数更接近，导致降低的接触电阻。 这提供了具有改进的性能特性的二极管。

公开(公告)号：US20090309164A1

公开(公告)日：2009-12-17

申请号：US12139764

申请日：2008-06-16

申请人： Xiangdong Chen ,  Haining S. Yang

发明人： Xiangdong Chen ,  Haining S. Yang

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823835 ,  H01L21/823807 ,  H01L29/7843

摘要： The present invention provides a semiconducting device including a substrate including a semiconducting surface having an n-type device in a first device region and a p-type device in a second device region, the n-type device including a first gate structure present overlying a portion of the semiconducting surface in the first device region including a first work function metal semiconductor alloy in the semiconducting surface adjacent to the portion of the semiconducting surface underlying the gate structure, and a first type strain inducing layer present overlying the first device region; and a p-type device including a second gate structure present overlying a portion of the semiconducting surface in the second device region including a second work function metal semiconductor alloy in the semiconducting surface adjacent to the portion of the semiconducting surface underlying the gate structure, and a second type strain inducing layer present overlying the second device region.

摘要翻译： 本发明提供了一种半导体器件，其包括：衬底，其包括在第一器件区域中具有n型器件的半导体表面和在第二器件区域中的p型器件，所述n型器件包括第一栅极结构， 所述第一器件区域中的所述半导体表面的部分包括与所述栅极结构下方的所述半导体表面的部分相邻的所述半导体表面中的第一功函数金属半导体合金，以及存在于所述第一器件区域上方的第一类型应变诱导层; 以及包括第二栅极结构的p型器件，所述第二栅极结构覆盖所述第二器件区域中的所述半导体表面的一部分，所述第二栅极结构包括与所述栅极结构的所述半导体表面的所述部分相邻的所述半导体表面中的第二功函数金属半导体合金， 存在覆盖在第二器件区域上的第二类型应变诱导层。

公开(公告)号：US07612414B2

公开(公告)日：2009-11-03

申请号：US11693254

申请日：2007-03-29

申请人： Xiangdong Chen ,  Jun Jung Kim ,  Young Gun Ko ,  Jae-Eun Park ,  Haining S. Yang

发明人： Xiangdong Chen ,  Jun Jung Kim ,  Young Gun Ko ,  Jae-Eun Park ,  Haining S. Yang

IPC分类号： H01L21/8238 ,  H01L23/18

CPC分类号： H01L21/0217 ,  H01L21/02274 ,  H01L21/3185 ,  H01L21/823807 ,  H01L29/7843

摘要： A semiconductor structure is provided which includes a first semiconductor device in a first active semiconductor region and a second semiconductor device in a second active semiconductor region. A first dielectric liner overlies the first semiconductor device and a second dielectric liner overlies the second semiconductor device, with the second dielectric liner overlapping the first dielectric liner at an overlap region. The second dielectric liner has a first portion having a first thickness contacting an apex of the second gate conductor and a second portion extending from peripheral edges of the second gate conductor which has a second thickness substantially greater than the first thickness. A first conductive via contacts at least one of the first or second gate conductors and the conductive via extends through the first and second dielectric liners at the overlap region. A second conductive via may contact at least one of a source region or a drain region of the second semiconductor device.

摘要翻译： 提供一种半导体结构，其包括第一有源半导体区域中的第一半导体器件和第二有源半导体区域中的第二半导体器件。 第一电介质衬垫覆盖在第一半导体器件上，并且第二电介质衬垫覆盖在第二半导体器件上，第二电介质衬垫在重叠区域与第一电介质衬垫重叠。 第二电介质衬垫具有第一部分，第一部分具有与第二栅极导体的顶点接触的第一厚度和从第二栅极导体的周边边延伸的第二部分，第二部分具有基本上大于第一厚度的第二厚度。 第一导电通孔接触第一或第二栅极导体和导电通孔中的至少一个延伸穿过第一和第二电介质衬垫在重叠区域。 第二导电通孔可以接触第二半导体器件的源极区域或漏极区域中的至少一个。

公开(公告)号：US20090108364A1

公开(公告)日：2009-04-30

申请号：US11924045

申请日：2007-10-25

申请人： Haining S. Yang ,  Xiangdong Chen

发明人： Haining S. Yang ,  Xiangdong Chen

IPC分类号： H01L29/94 ,  H01L21/8238

CPC分类号： H01L29/7391 ,  H01L27/0629 ,  H01L27/0811 ,  H01L27/0814 ,  H01L29/402 ,  H01L29/456 ,  H01L29/66356 ,  H01L29/861

摘要： A CMOS diode and method of making it are disclosed. In one embodiment, the diode comprises a silicon substrate having an N doped region and a P doped region. A first silicide region is formed on the N doped region of the silicon substrate, and a second silicide region formed on the P doped region of the silicon substrate. The first silicide region is comprised of a material having a bandgap value lower than the bandgap value of the material comprising the second silicide region. The result is a diode where the workfunction of each region of silicide more closely matches the workfunction of the doped silicon it contacts, resulting in reduced contact resistance. This provides for a diode with improved performance characteristics.

摘要翻译： 公开了一种CMOS二极管及其制造方法。 在一个实施例中，二极管包括具有N掺杂区域和P掺杂区域的硅衬底。 在硅衬底的N掺杂区域上形成第一硅化物区域，以及形成在硅衬底的P掺杂区域上的第二硅化物区域。 第一硅化物区域由具有低于包含第二硅化物区域的材料的带隙值的带隙值的材料构成。 结果是二极管，其中硅化物的每个区域的功函数与其接触的掺杂硅的功函数更接近，导致降低的接触电阻。 这提供了具有改进的性能特性的二极管。

公开(公告)号：US20080217665A1

公开(公告)日：2008-09-11

申请号：US11306745

申请日：2006-01-10

申请人： Xiangdong Chen ,  Haining S. Yang

发明人： Xiangdong Chen ,  Haining S. Yang

IPC分类号： H01L29/78 ,  H01L21/311

CPC分类号： H01L21/823807 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： A method for making a semiconductor device structure, includes: providing a substrate; forming on the substrate: a first layer below and second layers on a gate with spacers, source and drain regions adjacent to the gate, silicides on the gate and source and drain regions; disposing a stress layer over the structure resulting from the forming step; disposing an insulating layer over the stress layer; removing portions of the insulating layer to expose a top surface of the stress layer; removing the top surface and other portions of the stress layer and portions of the spacers to form a trench, and then disposing a suitable stress material into the trench.

摘要翻译： 一种制造半导体器件结构的方法，包括：提供衬底; 在衬底上形成：在栅极上的第一层和栅极上的第二层，具有间隔物，与栅极相邻的源极和漏极区域，栅极上的硅化物和源极和漏极区域; 在由成形步骤导致的结构上设置应力层; 在应力层上设置绝缘层; 去除绝缘层的部分以暴露应力层的顶表面; 去除应力层的顶表面和其它部分和间隔物的部分以形成沟槽，然后将合适的应力材料设置到沟槽中。