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公开(公告)号：US06469529B1
公开(公告)日：2002-10-22
申请号：US09580716
申请日：2000-05-30
IPC分类号： G01R31302
CPC分类号： G01R31/311
摘要： Integrated circuit devices are analyzed using an integrated system adapted to obtain time-resolved information from the back side of a silicon based semiconductor chip using hot carrier emissions. According to an example embodiment of the present invention, a system is adapted to analyze a semiconductor device under test (DUT) using a plurality of sensors mounted to a microscope having an objective lens. The plurality of sensors include a global acquisition sensor, a single-point acquisition sensor, and a navigation sensor. The integrated system is adapted to use the plurality of sensors individually and simultaneously. The integrated system improves the analysis of the DUT for reasons including that it makes possible the performance of more than one type of analysis simultaneously using a single test arrangement.
摘要翻译： 使用集成系统分析集成电路器件，该系统适于使用热载流子发射从硅基半导体芯片的背面获得时间分辨信息。 根据本发明的示例性实施例，系统适用于使用安装在具有物镜的显微镜上的多个传感器来分析被测半导体器件（DUT）。 多个传感器包括全局采集传感器，单点采集传感器和导航传感器。 集成系统适于单独和同时使用多个传感器。 集成系统改进了DUT的分析原因，包括使用单个测试装置可以同时执行多种类型的分析。
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公开(公告)号：US08187772B2
公开(公告)日：2012-05-29
申请号：US10961347
申请日：2004-10-08
CPC分类号： B82Y10/00 , G03F7/70325
摘要： Lithography using solid immersion lenses is disclosed. In one aspect, an apparatus is provided that includes a resist film that has a first side and a second and opposite side. One or more solid immersion lenses are positioned over the first side of the resist film. In another aspect, a method of manufacturing is provided that includes forming a resist film and exposing the resist film with radiation transmitted through one or more solid immersion lenses.
摘要翻译： 公开了使用固体浸没透镜的平版印刷术。 一方面，提供一种装置，其包括具有第一侧和第二相对侧的抗蚀剂膜。 一个或多个固体浸没透镜位于抗蚀剂膜的第一侧上。 在另一方面，提供了一种制造方法，其包括形成抗蚀剂膜并通过透射通过一个或多个固体浸没透镜的辐射曝光抗蚀剂膜。
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公开(公告)号：US20110037107A1
公开(公告)日：2011-02-17
申请号：US12539821
申请日：2009-08-12
IPC分类号： H01L31/101 , H01L31/18
CPC分类号： H01L31/113
摘要： A silicon photon detector device and methodology are provided for detecting incident photons in a partially depleted floating body SOI field-effect transistor (310) which traps charges created by visible and mid infrared light in a floating body region (304) when the silicon photon detector is configured in a detect mode, and then measures or reads the resulting enhanced drain current with a current detector in a read mode.
摘要翻译： 提供硅光子检测器装置和方法，用于在部分耗尽的浮体SOI场效应晶体管（310）中检测入射光子，该场效应晶体管（310）在硅光子检测器（310）捕获由浮动体区域（304）中的可见光和中红外光产生的电荷 被配置在检测模式中，然后在读取模式下用电流检测器测量或读取所得到的增强的漏极电流。
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公开(公告)号：US06891390B1
公开(公告)日：2005-05-10
申请号：US10086505
申请日：2002-02-28
IPC分类号： G01Q60/00 , G01R31/303 , G01R31/26
CPC分类号： G01R31/303 , Y10S977/854
摘要： Circuitry within a semiconductor die is analyzed by applying an electric field without necessarily directly accessing the circuitry. According to an example embodiment of the present invention, an electric field is applied to a semiconductor die and used to stimulate circuitry therein. A response of the die to the electric field is detected and used to detect an electrical characteristic of the die. This is particularly useful in applications where it is desired to direct stimulation to the die on a nanoscale level, such as when using a fine probe tip (e.g., a scanning probe microscope tip) to apply the electric field. In this manner, the response of the die can be mapped to circuitry within a few nanometers of the probe tip.
摘要翻译： 通过施加电场来分析半导体管芯内的电路，而不必直接访问电路。 根据本发明的示例性实施例，电场被施加到半导体管芯并且用于在其中刺激电路。 检测模具对电场的响应并用于检测管芯的电特性。 这在用于在纳米尺度上直接刺激模具的应用中尤其有用，例如当使用细探针尖端（例如扫描探针显微镜尖端）施加电场时。 以这种方式，管芯的响应可以映射到探针尖端的几纳米内的电路。
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公开(公告)号：US06833716B1
公开(公告)日：2004-12-21
申请号：US10113620
申请日：2002-03-29
IPC分类号： G01R3126
CPC分类号： G01R31/311 , G01R1/071
摘要： An integrated circuit die having silicon on insulator (SOI) structure is analyzed in a manner that improves the ability to obtain a signal from the SOI structure. According to one example embodiment, a stimulating device is adapted to stimulate an integrated circuit having SOI structure. An electro-optic probe arrangement is focused on a selected portion of the integrated circuit in a manner that makes possible the detection of a response to the stimulation from the SOI selected portion. In this manner electro-optic probing portions of an integrated circuit having SOI structure is enhanced.
摘要翻译： 以提高从SOI结构获得信号的能力的方式分析具有绝缘体上硅（SOI）结构的集成电路芯片。 根据一个示例实施例，刺激装置适于刺激具有SOI结构的集成电路。 电光探针装置以能够从SOI选择部分检测对刺激的响应成为可能的方式聚焦在集成电路的选定部分上。 以这种方式增强了具有SOI结构的集成电路的电光探测部分。
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公开(公告)号：US06657446B1
公开(公告)日：2003-12-02
申请号：US09409974
申请日：1999-09-30
IPC分类号： G01R31302
CPC分类号： G01R31/311
摘要： An apparatus, system, and method are provided for testing an integrated circuit with a probe card having optical fibers. The optical fibers of the probe card are fixed in alignment with test structures in the integrated circuit, and each optical fiber is coupled to an avalanche photo-diode for measuring photoemissions from the test structures. The photoemissions can be analyzed to verify correct circuit behavior. The optical fibers can be alternatives or complements to electrically conductive probes of the probe card.
摘要翻译： 提供了一种用具有光纤的探针卡测试集成电路的装置，系统和方法。 探针卡的光纤与集成电路中的测试结构对准固定，并且每个光纤耦合到雪崩光电二极管，用于测量来自测试结构的光电发射。 可以分析光电检测以验证电路的正确行为。 光纤可以是探针卡的导电探针的替代或补充。
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公开(公告)号：US06621288B1
公开(公告)日：2003-09-16
申请号：US09864665
申请日：2001-05-23
IPC分类号： G01R3126
CPC分类号： G01R31/307
摘要： Analysis of a semiconductor die having silicon-on-insulator (SOI) structure is enhanced by operating a die and detecting a response that is used to analyze selected characteristics of the die. According to an example embodiment of the present invention, a die having a thinned backside is provided for analysis. The die is operated so that one or more portions of circuitry in the die are near a state-changing transition between a failed mode and a recovered mode. An electron-beam probe is directed to the thinned backside, and the probe electrically couples a capacitance load to underlying circuitry via the insulator of the SOI structure. The capacitance load alters the timing margin of a portion of the circuitry and, thereby, causes the circuitry to undergo a state-changing transition. A response from the circuitry related to the transition is detected and used to analyze the die. In this manner, portions of the die being affected by altered timing margins can be detected.
摘要翻译： 通过操作管芯并检测用于分析所选择的管芯特性的响应来增强具有绝缘体上硅（SOI）结构的半导体管芯的分析。 根据本发明的示例性实施例，提供具有变薄的背面的模具用于分析。 管芯的操作使得管芯中的一个或多个电路部分接近故障模式和恢复模式之间的状态转变。 电子束探针被引导到减薄的背面，并且探针经由SOI结构的绝缘体将电容负载电耦合到底层电路。 电容负载改变电路的一部分的定时裕度，从而使电路经历状态变化的转变。 检测到与转换有关的电路的响应并用于分析芯片。 以这种方式，可以检测到模具受到更改的定时裕度影响的部分。
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公开(公告)号：US06566888B1
公开(公告)日：2003-05-20
申请号：US09833250
申请日：2001-04-11
IPC分类号： G01R3108
CPC分类号： H01L22/22 , H01L21/76894
摘要： The present invention is directed to the repair of resistive circuitry in an integrated circuit die having a multitude of circuit paths. According to an example embodiment of the present invention, a semiconductor die having a resistive electrical connection is analyzed. The location of a circuit portion in the die having a resistive electrical connection is identified. Using the identified location, the resistive circuit portion is annealed and the resistivity of that circuit portion is reduced. The reduced resistivity improves the ability of the die to operate at high speeds, and makes possible the repair and subsequent use of the die in various applications.
摘要翻译： 本发明涉及具有多个电路路径的集成电路管芯中的电阻电路的修复。 根据本发明的示例性实施例，分析具有电阻电连接的半导体管芯。 识别具有电阻电连接的管芯中的电路部分的位置。 使用识别的位置，对电阻电路部分进行退火，并减小该电路部分的电阻率。 降低的电阻率提高了模具在高速下运行的能力，并且使得可以在各种应用中修复和随后使用模具。
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公开(公告)号：US07884633B2
公开(公告)日：2011-02-08
申请号：US12133305
申请日：2008-06-04
IPC分类号： G01R31/26
CPC分类号： G01R31/311
摘要： Various apparatus and methods of testing a semiconductor chip for soft defects are disclosed. In one aspect, a method of testing a semiconductor chip that has a surface and plural circuit structures positioned beneath the surface is provided. An external stimulus is applied to a series of fractional portions of the surface to perturb portions of the plural circuit structures such that at least one of the series of fractional portions is smaller than another of the series of fractional portions. The semiconductor chip is caused to perform a test pattern during the application of external stimulus to each of the fractional portions to determine if a soft defect exists in any of the series of fractional portions.
摘要翻译： 公开了测试用于软缺陷的半导体芯片的各种装置和方法。 在一个方面，提供一种测试半导体芯片的方法，该半导体芯片具有位于表面下方的表面和多个电路结构。 外部刺激被施加到表面的一系列分数部分以扰乱多个电路结构的部分，使得该系列分数部分中的至少一个小于该系列分数部分中的另一个。 使半导体芯片在向每个分数部分施加外部刺激期间执行测试图案，以确定在任何一系列分数部分中是否存在软缺陷。
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公开(公告)号：US20110134520A1
公开(公告)日：2011-06-09
申请号：US12653235
申请日：2009-12-09
申请人： Rama R. Goruganthu
发明人： Rama R. Goruganthu
CPC分类号： G02F1/093 , G01N21/956 , G02B21/0016 , G02B21/10 , G02B27/28 , G02F2201/58 , G02F2203/07
摘要： According to one embodiment, an optical isolation module comprises first and second linear polarizers, a Faraday rotator situated between the first and second linear polarizers and a transmissive element including a half-wave plate also situated between the first and second linear polarizers. In one embodiment, a method for performing optical isolation comprises rotating an axis of polarization of a linearly polarized light beam by a first rotation in a first direction, and selectively rotating a portion of the linearly polarized light beam by a second rotation in the first direction to produce first and second linearly polarized light beam portions. As a result, the first linearly polarized light beam portion undergoes the first rotation, and the second linearly polarized light beam portion undergoes the first and second rotations. The method further comprises filtering one of the first and second linearly polarized light beam portions to produce a light annulus.
摘要翻译： 根据一个实施例，光隔离模块包括第一和第二线性偏振器，位于第一和第二线性偏振器之间的法拉第旋转器和包括也位于第一和第二线性偏振器之间的半波片的透射元件。 在一个实施例中，一种执行光学隔离的方法包括：使第一方向上的第一旋转使线性偏振光束的偏振轴旋转，并且通过第一方向上的第二旋转选择性地旋转一部分线偏振光束 以产生第一和第二直线偏振光束部分。 结果，第一直线偏振光束部分经历第一旋转，并且第二线偏振光束部分经历第一和第二旋转。 该方法还包括对第一和第二直线偏振光束部分之一进行滤波以产生光环。
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