公开(公告)号：US07496673B2

公开(公告)日：2009-02-24

申请号：US11065707

申请日：2005-02-24

申请人： Michael Karl Gschwind ,  Harm Peter Hofstee ,  Martin E. Hopkins ,  James Allan Kahle

发明人： Michael Karl Gschwind ,  Harm Peter Hofstee ,  Martin E. Hopkins ,  James Allan Kahle

IPC分类号： G06F15/16

CPC分类号： G06F9/4862 ,  G06F15/16 ,  H04L29/06027 ,  H04L63/168 ,  H04L67/10 ,  H04L67/34

摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

摘要翻译： 提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。 该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。 公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。 还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。 提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。 统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。 每个软件单元在网络上唯一标识。

公开(公告)号：US20080256275A1

公开(公告)日：2008-10-16

申请号：US12049323

申请日：2008-03-15

申请人： Harm Peter Hofstee ,  Charles Ray Johns ,  James Allan Kahle

发明人： Harm Peter Hofstee ,  Charles Ray Johns ,  James Allan Kahle

IPC分类号： G06F13/00

CPC分类号： G06F9/4862 ,  G06F15/16 ,  H04L29/06027 ,  H04L63/168 ,  H04L67/10 ,  H04L67/34

摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

摘要翻译： 提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。 该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。 公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。 还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。 提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。 统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。 每个软件单元在网络上唯一标识。

公开(公告)号：US20080235647A1

公开(公告)日：2008-09-25

申请号：US12130268

申请日：2008-05-30

申请人： Harm Peter Hofstee ,  James Allan Kahle ,  Takeshi Yamazaki

发明人： Harm Peter Hofstee ,  James Allan Kahle ,  Takeshi Yamazaki

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： Disclosed is a procedure or design approach for functional modules that may be used in connection with a multiprocessor integrated circuit chip. The approach includes keeping the dimensions of each module substantially the same and having the bus, power, clock and I/O connection configured the same on all modules. Further requirements for ease of use are to generalize the capability of each module as much as possible and to decentralize functions such as testing to be primarily performed within each module. The use of such considerations or rules substantially eases the design of a given type of custom chips, and based upon an initial chip design greatly facilitates the design of further custom chips, similar in application, but subsequent to the successful completion of the initial chip. The standardization modules and replication of the modules on a given chip also reduces physical verification time in initial chip design as well as redesign time of the initial chip when requirements for chip capability are redefined or otherwise changed. Any subsequent or further custom chips can include more or less of specific modules based upon already established parameters.

摘要翻译： 公开了可以与多处理器集成电路芯片结合使用的功能模块的过程或设计方法。 该方法包括保持每个模块的尺寸基本相同，并使总线，电源，时钟和I / O连接在所有模块上配置相同。 对易用性的进一步要求是尽可能地推广每个模块的能力，并将诸如测试之类的功能分散在每个模块内主要执行。 这种考虑或规则的使用大大简化了给定类型的定制芯片的设计，并且基于初始的芯片设计极大地促进了其他定制芯片的设计，其应用类似，但是在初始芯片的成功完成之后。 给定芯片上的标准化模块和模块的复制也减少了初始芯片设计中的物理验证时间，以及在重新定义或改变芯片能力要求时初始芯片的重新设计时间。 任何后续或进一步的定制芯片可以基于已经建立的参数包括或多或少的特定模块。

公开(公告)号：US07398482B2

公开(公告)日：2008-07-08

申请号：US11191580

申请日：2005-07-28

申请人： Harm Peter Hofstee ,  James Allan Kahle ,  Takeshi Yamazaki

发明人： Harm Peter Hofstee ,  James Allan Kahle ,  Takeshi Yamazaki

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： Disclosed is a procedure or design approach for functional modules that may be used in connection with a multiprocessor integrated circuit chip. The approach includes keeping the dimensions of each module substantially the same and having the bus, power, clock and I/O connection configured the same on all modules. Further requirements for ease of use are to generalize the capability of each module as much as possible and to decentralize functions such as testing to be primarily performed within each module. The use of such considerations or rules substantially eases the design of a given type of custom chips, and based upon an initial chip design greatly facilitates the design of further custom chips, similar in application, but subsequent to the successful completion of the initial chip. The standardization modules and replication of the modules on a given chip also reduces physical verification time in initial chip design as well as redesign time of the initial chip when requirements for chip capability are redefined or otherwise changed. Any subsequent or further custom chips can include more or less of specific modules based upon already established parameters.

摘要翻译： 公开了可以与多处理器集成电路芯片结合使用的功能模块的过程或设计方法。 该方法包括保持每个模块的尺寸基本相同，并使总线，电源，时钟和I / O连接在所有模块上配置相同。 对易用性的进一步要求是尽可能地推广每个模块的能力，并将诸如测试之类的功能分散在每个模块内主要执行。 这种考虑或规则的使用大大简化了给定类型的定制芯片的设计，并且基于初始的芯片设计极大地促进了其他定制芯片的设计，其应用类似，但是在初始芯片的成功完成之后。 给定芯片上的标准化模块和模块的复制也减少了初始芯片设计中的物理验证时间，以及在重新定义或改变芯片能力要求时初始芯片的重新设计时间。 任何后续或进一步的定制芯片可以基于已经建立的参数包括或多或少的特定模块。

公开(公告)号：US07114042B2

公开(公告)日：2006-09-26

申请号：US10443727

申请日：2003-05-22

申请人： Michael Norman Day ,  Charles Ray Johns ,  James Allan Kahle ,  Peichum Peter Liu ,  Thuong Quang Truong

发明人： Michael Norman Day ,  Charles Ray Johns ,  James Allan Kahle ,  Peichum Peter Liu ,  Thuong Quang Truong

IPC分类号： G06F13/00

CPC分类号： G06F13/28 ,  G06F9/3004 ,  G06F9/30087 ,  G06F12/0831 ,  G06F2213/0038

摘要： The present invention provides for atomic update primitives in an asymmetric single-chip heterogeneous multiprocessor computer system having a shared memory with DMA transfers. At least one lock line command is generated from a set comprising a get lock line command with reservation, a put lock line conditional command, and a put lock line unconditional command.

摘要翻译： 本发明提供了具有具有DMA传输的共享存储器的非对称单芯片异构多处理器计算机系统中的原子更新原语。 从包括具有预留的get lock line命令，put lock line条件命令和put lock line无条件命令的集合中生成至少一个lock line命令。

公开(公告)号：US07093080B2

公开(公告)日：2006-08-15

申请号：US10682386

申请日：2003-10-09

申请人： Michael Norman Day ,  Harm Peter Hofstee ,  Charles Ray Johns ,  James Allan Kahle ,  David J. Shippy ,  Thuong Quang Truong

发明人： Michael Norman Day ,  Harm Peter Hofstee ,  Charles Ray Johns ,  James Allan Kahle ,  David J. Shippy ,  Thuong Quang Truong

IPC分类号： G06F12/00

CPC分类号： G06F12/0835

摘要： Disclosed is a coherent cache system that operates in conjunction with non-homogeneous processing units. A set of processing units of a first configuration has conventional cache and directly accesses common or shared system physical and virtual address memory through the use of a conventional MMU (Memory Management Unit). Additional processors of a different configuration and/or other devices that need to access system memory are configured to store accessed data in compatible caches. Each of the caches is compatible with a given protocol coherent memory management bus interspersed between the caches and the system memory.

摘要翻译： 公开了与非均匀处理单元结合操作的一致的缓存系统。 一组第一配置的处理单元具有常规高速缓存，并且通过使用常规MMU（存储器管理单元）直接访问公用或共享系统物理和虚拟地址存储器。 需要访问系统存储器的不同配置和/或其他设备的其他处理器被配置为将访问的数据存储在兼容的高速缓存中。 每个缓存与散列在高速缓存和系统存储器之间的给定协议相干存储器管理总线兼容。

公开(公告)号：US06931493B2

公开(公告)日：2005-08-16

申请号：US10346294

申请日：2003-01-16

申请人： Charles Ray Johns ,  James Allan Kahle ,  Peichun Peter Liu

发明人： Charles Ray Johns ,  James Allan Kahle ,  Peichun Peter Liu

IPC分类号： G06F12/12 ,  G06F12/08

CPC分类号： G06F12/123 ,  G06F12/128

摘要： The present invention provides for determining an MRU or LRU way of a partitioned cache. The partitioned cache has a plurality of ways. There are a plurality of partitions, each partition comprising at least one way. An updater is employable to update a logic table as a function of an access of a way. Partition comparison logic is employable to determine whether two ways are members of the same partition, and to allow the comparison of the ways correlating to a first matrix indices and a second matrix indices. An intersection generator is employable to create an intersection box of the memory table as a function of a first and second matrix indices. Access order logic is employable to combine the output of the intersection generator, thereby determining which way is the most or least recently used way.

摘要翻译： 本发明提供用于确定分区高速缓存的MRU或LRU方式。 分区缓存具有多种方式。 存在多个分区，每个分区包括至少一个方式。 更新器可用于根据方式的访问来更新逻辑表。 分区比较逻辑可用于确定两种方式是否是相同分区的成员，并且允许比较与第一矩阵索引和第二矩阵索引相关的方式。 交叉点生成器可用于根据第一和第二矩阵索引创建存储表的交集框。 访问顺序逻辑可用于组合交叉发生器的输出，从而确定哪种方式是最近或最近最少使用的方式。

公开(公告)号：US06785841B2

公开(公告)日：2004-08-31

申请号：US09734371

申请日：2000-12-14

申请人： Chekib Akrout ,  Harm Peter Hofstee ,  James Allan Kahle

发明人： Chekib Akrout ,  Harm Peter Hofstee ,  James Allan Kahle

IPC分类号： G06F1100

CPC分类号： G06F11/2043 ,  G06F11/2028 ,  G06F11/2038

摘要： A system including a central processor and a plurality of attached processors all on a single die are disclosed. Each of the attached processors is preferably functionally equivalent to each of the other attached processors. The system further includes at least one redundant processor that is connectable to the central processor. The redundant processor may be substantially equivalent to each of the attached processors. Upon detecting a failure in one of the attached processors, the system is configured to disable the non-functional processor and enable the redundant processor. The attached processors may be connected to a memory interface unit via a parallel bus or a pipelined bus in which each attached processor is connected to a stage of the pipelined bus. The attached processors may each include a load/store unit and logic suitable for performing a mathematical function.

摘要翻译： 公开了一种包括中央处理器和多个附属处理器的系统，其全部在单个管芯上。 每个连接的处理器优选地在功能上等同于其他附加处理器中的每一个。 该系统还包括可连接到中央处理器的至少一个冗余处理器。 冗余处理器可以基本上等同于附接的每个处理器。 一旦检测到所附加的处理器之一的故障，则该系统被配置为禁用非功能处理器并启用冗余处理器。 连接的处理器可以经由并行总线或流水线总线连接到存储器接口单元，其中每个连接的处理器连接到流水线总线的级。 附加的处理器可以各自包括适于执行数学功能的加载/存储单元和逻辑。

公开(公告)号：US06725354B1

公开(公告)日：2004-04-20

申请号：US09594631

申请日：2000-06-15

申请人： James Allan Kahle ,  Charles Roberts Moore

发明人： James Allan Kahle ,  Charles Roberts Moore

IPC分类号： G06F900

CPC分类号： G06F9/3017 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3857 ,  G06F9/3879 ,  G06F9/3885 ,  G06F15/7832

摘要： A microprocessor includes a first processor core and a second processor core. The first core includes a first processing block. The first processing block includes an execution unit suitable for executing a first type of instruction. The second core includes a second processing block. The second processing block includes an execution unit suitable for executing an instruction if the instruction is of the first type. The processor further includes a shared execution unit. The first and second processor cores are adapted to forward an instruction to the shared execution unit for execution if the instruction is of a second type. In one embodiment, the first type of instruction includes fixed point instructions, load/store instructions, and branch instructions and the second type of instruction includes floating point instructions.

摘要翻译： 微处理器包括第一处理器核和第二处理器核。 第一核心包括第一处理块。 第一处理块包括适于执行第一类型的指令的执行单元。 第二核心包括第二处理块。 第二处理块包括执行单元，如果指令是第一类型，则适合于执行指令。 处理器还包括共享执行单元。 如果指令是第二类型，则第一和第二处理器核心适于将指令转发到共享执行单元以执行。 在一个实施例中，第一类型的指令包括固定点指令，加载/存储指令和分支指令，并且第二类型的指令包括浮点指令。

公开(公告)号：US5926628A

公开(公告)日：1999-07-20

申请号：US892723

申请日：1997-07-15

申请人： Cang Ngoc Tran ,  James Allan Kahle

发明人： Cang Ngoc Tran ,  James Allan Kahle

IPC分类号： G06F13/364 ,  G06F13/36

CPC分类号： G06F13/364

摘要： A method and system for arbitrating access to a component of a computer have been disclosed the method and system include an arbitration unit for granting access to the component; and a plurality of units for executing a plurality of transactions requiring access to the component. Each transaction of the plurality of transactions has an encoded priority. Each of the plurality of units further provide the arbitration unit with the encoded priority of each of the plurality of transactions. The arbitration unit grants a predetermined number of the plurality of units access to the component in response to the encoded priority of each of the predetermined plurality of transactions.

摘要翻译： 已经公开了一种用于仲裁对计算机的组件的访问的方法和系统，所述方法和系统包括用于授予访问组件的仲裁单元; 以及用于执行需要访问该组件的多个事务的多个单元。 多个事务的每个事务具有编码的优先级。 多个单元中的每一个还向仲裁单元提供多个交易中的每一个的编码优先级。 仲裁单元响应于每个预定多个事务的编码优先级，向该组件授予多个单元的预定数量的访问。