-
公开(公告)号：US20220059763A1
公开(公告)日：2022-02-24
申请号：US17480694
申请日：2021-09-21
Applicant: Micron Technology, Inc.
Inventor： Agostino Pirovano , Kolya Yastrebenetsky , Anna Maria Conti , Fabio Pellizzer
Abstract: Methods, systems, and devices for memory cells with asymmetrical electrode interfaces are described. A memory cell with asymmetrical electrode interfaces may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a top surface area in contact with a top electrode and a bottom surface area in contact with a bottom electrode, where the top surface area in contact with the top electrode is a different size than the bottom surface area in contact with the bottom electrode.
-
公开(公告)号：US11133463B2
公开(公告)日：2021-09-28
申请号：US16856631
申请日：2020-04-23
Applicant: Micron Technology, inc.
Inventor： Agostino Pirovano , Kolya Yastrebenetsky , Anna Maria Conti , Fabio Pellizzer
Abstract: Methods, systems, and devices for memory cells with asymmetrical electrode interfaces are described. A memory cell with asymmetrical electrode interfaces may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a top surface area in contact with a top electrode and a bottom surface area in contact with a bottom electrode, where the top surface area in contact with the top electrode is a different size than the bottom surface area in contact with the bottom electrode.
-
公开(公告)号：US11011582B2
公开(公告)日：2021-05-18
申请号：US16785026
申请日：2020-02-07
Applicant: Micron Technology, Inc.
Inventor： Anna Maria Conti , Andrea Redaelli , Agostino Pirovano
Abstract: An example three-dimensional (3-D) memory array includes a first plurality of conductive lines separated from one other by an insulation material, a second plurality of conductive lines, and a plurality of pairs of conductive pillars arranged to extend substantially perpendicular to the first plurality of conductive lines and the second plurality of conductive lines. The conductive pillars of each respective pair are coupled to a same conductive line of the second plurality of conductive lines. A storage element material is formed partially around the conductive pillars of each respective pair.
-
公开(公告)号：US20210119123A1
公开(公告)日：2021-04-22
申请号：US17088253
申请日：2020-11-03
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli , Anna Maria Conti , Agostino Pirovano
Abstract: Methods, systems, and devices for a tapered cell profile and fabrication are described. A memory storage component may contain multiple chalcogenide materials and may include a tapered profile. For example, a first chalcogenide material may be coupled with a second chalcogenide material. Each of the chalcogenide materials may be further coupled with a conductive material (e.g., an electrode). Through an etching process, the chalcogenide materials may tapered (e.g., step tapered). A pulse may be applied to the tapered chalcogenide materials resulting in a memory storage component that includes a mixture of the chalcogenide materials.
-
公开(公告)号：US20200321522A1
公开(公告)日：2020-10-08
申请号：US16856631
申请日：2020-04-23
Applicant: Micron Technology, Inc.
Inventor： Agostino Pirovano , Kolya Yastrebenetsky , Anna Maria Conti , Fabio Pellizzer
Abstract: Methods, systems, and devices for memory cells with asymmetrical electrode interfaces are described. A memory cell with asymmetrical electrode interfaces may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a top surface area in contact with a top electrode and a bottom surface area in contact with a bottom electrode, where the top surface area in contact with the top electrode is a different size than the bottom surface area in contact with the bottom electrode.
-
Patent Agency Ranking
公开(公告)号：US20200119273A1
公开(公告)日：2020-04-16
申请号：US16706358
申请日：2019-12-06
Applicant: Micron Technology, Inc.
Inventor： Agostino Pirovano , Kolya Yastrebenetsky , Anna Maria Conti , Fabio Pellizzer
Abstract: Methods, systems, and devices for memory cells with asymmetrical electrode interfaces are described. A memory cell with asymmetrical electrode interfaces may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a top surface area in contact with a top electrode and a bottom surface area in contact with a bottom electrode, where the top surface area in contact with the top electrode is a different size than the bottom surface area in contact with the bottom electrode.
-
公开(公告)号：US10461128B2
公开(公告)日：2019-10-29
申请号：US15497503
申请日：2017-04-26
Applicant: Micron Technology, Inc.
Inventor： Anna Maria Conti , Agostino Pirovano , Andrea Redaelli
Abstract: A method of forming an array of memory cells, where the array comprises an elevationally-inner tier of memory cells comprising spaced-inner-tier-lower-first-conductive lines and inner-tier-programmable material directly there-above, an elevationally-outer tier of memory cells comprising spaced-outer-tier-lower-first-conductive lines and outer-tier-programmable material directly there-above, and spaced-upper-second-conductive lines that are electrically shared by the outer-tier memory cells and the inner-tier memory cells, comprises depositing conductor material for all of the shared-spaced-upper-second-conductive lines. All of the conductor material for all of the shared-spaced-upper-second-conductive lines is patterned using only a single masking step. Other method embodiments and arrays of memory cells independent of method of manufacture are disclosed.
-
公开(公告)号：US20190252606A1
公开(公告)日：2019-08-15
申请号：US15893108
申请日：2018-02-09
Applicant: Micron Technology, Inc.
Inventor： Agostino Pirovano , Kolya Yastrebenetsky , Anna Maria Conti , Fabio Pellizzer
Abstract: Methods, systems, and devices for memory cells with asymmetrical electrode interfaces are described. A memory cell with asymmetrical electrode interfaces may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a top surface area in contact with a top electrode and a bottom surface area in contact with a bottom electrode, where the top surface area in contact with the top electrode is a different size than the bottom surface area in contact with the bottom electrode.
-
公开(公告)号：US10153194B2
公开(公告)日：2018-12-11
申请号：US15584413
申请日：2017-05-02
Applicant: Micron Technology, Inc.
Inventor： Marcello D. Mariani , Anna Maria Conti , Sara Vigano
IPC: H01L21/8234 , H01L21/762 , H01L29/78 , H01L29/744 , H01L21/308 , H01L21/8249 , H01L29/66 , H01L21/8239 , H01L27/102 , H01L21/8229 , H01L27/105 , H01L29/423 , H01L29/749
Abstract: An array of gated devices includes a plurality of gated devices arranged in rows and columns and individually including an elevationally inner region, a mid region elevationally outward of the inner region, and an elevationally outer region elevationally outward of the mid region. A plurality of access lines are individually laterally proximate the mid regions along individual of the rows. A plurality of data/sense lines are individually elevationally outward of the access lines and electrically coupled to the outer regions along individual of the columns. A plurality of metal lines individually extends along and between immediately adjacent of the rows elevationally inward of the access lines. The individual metal lines are directly against and electrically coupled to sidewalls of the inner regions of each of immediately adjacent of the rows. The metal lines are electrically isolated from the data/sense lines. Other arrays of gated devices and methods of forming arrays of gated devices are disclosed.
-
公开(公告)号：US09673054B2
公开(公告)日：2017-06-06
申请号：US14461751
申请日：2014-08-18
Applicant: Micron Technology, Inc.
Inventor： Marcello Mariani , Anna Maria Conti , Sara Vigano
IPC: H01L21/8249 , H01L21/308 , H01L29/78 , H01L29/744 , H01L27/102
CPC classification number: H01L21/76224 , H01L21/308 , H01L21/8229 , H01L21/823437 , H01L21/823475 , H01L21/823487 , H01L21/8239 , H01L21/8249 , H01L27/1022 , H01L27/1027 , H01L27/1052 , H01L29/4236 , H01L29/42364 , H01L29/66333 , H01L29/66363 , H01L29/66666 , H01L29/744 , H01L29/749 , H01L29/7827
Abstract: An array of gated devices includes a plurality of gated devices arranged in rows and columns and individually including an elevationally inner region, a mid region elevationally outward of the inner region, and an elevationally outer region elevationally outward of the mid region. A plurality of access lines are individually laterally proximate the mid regions along individual of the rows. A plurality of data/sense lines are individually elevationally outward of the access lines and electrically coupled to the outer regions along individual of the columns. A plurality of metal lines individually extends along and between immediately adjacent of the rows elevationally inward of the access lines. The individual metal lines are directly against and electrically coupled to sidewalls of the inner regions of each of immediately adjacent of the rows. The metal lines are electrically isolated from the data/sense lines. Other arrays of gated devices and methods of forming arrays of gated devices are disclosed.
-
-
-
-
-
-
-
-
-
Search Results
65
records
(took 0.032 seconds)
