公开(公告)号：US20220382487A1

公开(公告)日：2022-12-01

申请号：US17771668

申请日：2019-12-31

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer ,  Xinghui Duan ,  Massimo Zucchinali

IPC: G06F3/06 ,  G06F12/02

Abstract: A computing system (100) having a storage system that includes a storage device (130) and a host device (105), where the host device (105) is configured to issue memory access commands to the storage device (130). The computing system (100) further includes a prediction system (190) comprising processing circuitry that is configured to perform operations that cause the prediction system (190) to identify one or more components of the storage system (918) that limit random rad performance of the storage system (918). The operations further cause the prediction system (190) to obtain characterization data that is indicative of the impact of the one or more components on random read performance and generate a model based on the characterization data to predict random read performance of the storage system (918). The operations additionally cause the prediction system (190) to execute the model in a simulation of the storage system (918) to generate a random read performance parameter for the storage system (918).

公开(公告)号：US20220327019A1

公开(公告)日：2022-10-13

申请号：US17851782

申请日：2022-06-28

Applicant: Micron Technology, Inc.

Inventor： Jonathan Scott Parry ,  Nadav Grosz ,  David Aaron Palmer ,  Christian M. Gyllenskog

IPC: G06F11/10 ,  G06F3/06 ,  G06F12/02

Abstract: Apparatus and methods are disclosed, including using a memory controller to monitor at least one parameter related to power level of a host processor of a host device, and dynamically adjusting at least one of a clock frequency and a voltage level of an error-correcting code (ECC) subsystem of the memory controller based on the at least one parameter to control power usage of the host device.

公开(公告)号：US11467763B2

公开(公告)日：2022-10-11

申请号：US17153068

申请日：2021-01-20

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G06F3/06 ,  G06F12/10

Abstract: Methods, systems, and devices for valid data aware media reliability scanning are described. An apparatus may include a memory array comprising a plurality of blocks and a controller coupled with the memory array. The controller may be configured to select a block of the plurality of blocks for a scan operation to determine a margin of reliability for a first set of data stored in the block. The controller may identify information associated with a status of a validity of sub-blocks of the first set of data in the block. The controller may determine a first subset of the sub-blocks storing valid data of the first set of data and a second subset of sub-blocks that are invalid based on identifying the information. The controller may perform the scan operation on the first subset of sub-blocks and not on the second subset of sub-blocks in the block.

公开(公告)号：US20220229580A1

公开(公告)日：2022-07-21

申请号：US17153547

申请日：2021-01-20

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G06F3/06

Abstract: Methods, systems, and devices for temperature tracking for a memory system are described. A set of temperature ranges and a set of partitions of a memory system may be stored. Each temperature range of the set of temperature ranges may be mapped to one or more respective partitions of the set of partitions of the memory system. A command to read a partition of the set of partitions may be received. It may then be determined whether temperature data associated with the set of temperature ranges for the partition indicates that data was written to the partition outside a threshold temperature. Data may then be read from the partition based on having determined whether the temperature data associated with the set of temperature ranges indicates that the data was written to the partition outside of the threshold temperature.

公开(公告)号：US20220228925A1

公开(公告)日：2022-07-21

申请号：US17153107

申请日：2021-01-20

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G01K1/022 ,  G06F16/2455 ,  G05B19/042 ,  G01K1/02

Abstract: Methods, systems, and devices for temperature exception tracking in a temperature log for a memory system are described. The memory system may store the temperature log separate from data to which the temperature information corresponds. For example, a memory device may store data in a relatively higher-level cell and the corresponding temperature information in a relatively lower-level cell. To perform a write operation, the memory system may determine a current temperature at which the data is being written or was written to a partition of a memory device and may indicate in the temperature log if the current temperature is entering a temperature range that is outside a threshold temperature (e.g., a nominal temperature). To perform a read operation, the memory system may determine if the data to read was written to the memory device outside the threshold temperature to determine whether to perform temperature compensation for the read operation.

公开(公告)号：US20220214821A1

公开(公告)日：2022-07-07

申请号：US17702217

申请日：2022-03-23

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer ,  Sean L. Manion ,  Jonathan Scott Parry ,  Stephen Hanna ,  Qing Liang ,  Nadav Grosz ,  Chistian M. Gyllenskog ,  Kulachet Tanpairoj

IPC: G06F3/06 ,  G06F12/02

Abstract: Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.

公开(公告)号：US20220206959A1

公开(公告)日：2022-06-30

申请号：US17576466

申请日：2022-01-14

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G06F12/14 ,  G06F12/06 ,  G06F21/60

Abstract: Devices and techniques are disclosed herein for verifying host generated physical addresses at a memory device during a host-resident FTL mode of operation to ameliorate erroneous or potentially malicious access to the memory device.

公开(公告)号：US11295806B2

公开(公告)日：2022-04-05

申请号：US16554247

申请日：2019-08-28

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G11C11/409 ,  G06F12/02 ,  G06F12/14 ,  G06F3/06

Abstract: Devices and techniques are disclosed herein for more efficiently exchanging large amounts of data between a host and a flash storage system. In an example, read commands or write commands can optionally include a file-type indicator. The file-type indicator can allow for exchange of data between the host and the flash storage system using a single record of a Flash Translation Layer (FTL) table or logical-to-physical (L2P) table, and where the amount of data can be much larger than the atomic unit associated with the flash storage system.

公开(公告)号：US11294767B2

公开(公告)日：2022-04-05

申请号：US17100622

申请日：2020-11-20

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G06F11/00 ,  G11C29/00 ,  G06F11/10 ,  G06F3/06

Abstract: Aspects of the present disclosure configure a system component, such as memory sub-system controller, to defer performance of an error-correction parity calculation for a block of a memory components of the memory subsystem. In particular, a memory sub-system controller of some embodiments can defer (e.g., delay) performance of an error-correction parity calculation and can defer the error-correction parity calculation such that it is performed at a time when the memory sub-system satisfies an idle state condition.

公开(公告)号：US20220091788A1

公开(公告)日：2022-03-24

申请号：US17540546

申请日：2021-12-02

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G06F3/06

Abstract: Devices and techniques for arbitrating operation of memory devices in a managed NAND memory system to conform the operation to a power budget. In an example, a method can include enabling a subset of memory die of a memory system having multiple memory die, starting an active timer for each active memory die, initializing execution of a buffered memory command at each active die based on a timestamp associated with the buffered memory command, and disabling a first memory die of the subset of memory die when the active timer for the first die expires to maintain compliance with a power budget of the memory system.