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    APPARATUSES AND METHODS FOR WRITING MASKED DATA TO A BUFFER
    41.
    发明申请
    APPARATUSES AND METHODS FOR WRITING MASKED DATA TO A BUFFER 有权
    将掩蔽数据写入BUFFER的设备和方法

    公开(公告)号：US20150170731A1

    公开(公告)日：2015-06-18

    申请号：US14133272

    申请日：2013-12-18

    Applicant: Micron Technology, Inc.

    Inventor： Parthasarathy Gajapathy ,  David R. Brown

    IPC: G11C11/4093

    CPC classification number: G11C11/4093 ,  G11C7/1009

    Abstract: Disclosed are apparatuses and methods for writing data to a memory array of a buffer. One such apparatus may include a multiplexer that receives data words and a data mask. The multiplexer may change the order of the data words to group masked data words together and to group unmasked data words together. The multiplexer may also change the order of the data mask to group masking bits together and to group unmasking bits together. The apparatus may use the data words with the changed order and the data mask with the changed order to write data to the memory array.

    Abstract translation: 公开了将数据写入缓冲器的存储器阵列的装置和方法。 一种这样的装置可以包括接收数据字和数据掩码的多路复用器。 复用器可以将数据字的顺序改变为将屏蔽的数据字组合在一起，并将未屏蔽的数据字组合在一起。 多路复用器还可以将数据掩码的顺序改变为组屏蔽位在一起，并且将未屏蔽位组合在一起。 设备可以使用具有改变顺序的数据字和具有改变顺序的数据掩码将数据写入存储器阵列。

    METHODS AND SYSTEMS FOR DETECTION IN A STATE MACHINE
    42.
    发明申请
    METHODS AND SYSTEMS FOR DETECTION IN A STATE MACHINE 有权
    用于状态机检测的方法和系统

    公开(公告)号：US20140325494A1

    公开(公告)日：2014-10-30

    申请号：US14329586

    申请日：2014-07-11

    Applicant: Micron Technology, Inc.

    Inventor： David R. Brown ,  Harold B Noyes

    IPC: G06F9/45

    CPC classification number: G06F9/444 ,  G06F8/45 ,  G06F9/4498 ,  G06K9/00986

    Abstract: A device including a data analysis element including a plurality of memory cells. The memory cells analyze at least a portion of a data stream and output a result of the analysis. The device also includes a detection cell. The detection cell includes an AND gate. The AND gate receives result of the analysis as a first input. The detection cell also includes a D flip-flop including an output coupled to a second input of the AND gate.

    Abstract translation: 一种包括包括多个存储单元的数据分析单元的设备。 存储器单元分析数据流的至少一部分并输出分析结果。 该装置还包括检测单元。 检测单元包括与门。 与门接收分析结果作为第一输入。 检测单元还包括D触发器，其包括耦合到与门的第二输入的输出。

    COUNTER OPERATION IN A STATE MACHINE LATTICE
    43.
    发明申请
    COUNTER OPERATION IN A STATE MACHINE LATTICE 有权
    状态机计数器中的计数器运行

    公开(公告)号：US20140115299A1

    公开(公告)日：2014-04-24

    申请号：US14143398

    申请日：2013-12-30

    Applicant: Micron Technology, Inc.

    Inventor： Harold B Noyes ,  David R. Brown ,  Paul Glendenning

    IPC: G06F15/82

    CPC classification number: G05B19/045 ,  G06F9/4498 ,  G06F15/82 ,  G06F21/567 ,  G06F2207/025 ,  G06N5/047 ,  H03K19/17724 ,  H03K19/17748

    Abstract: Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may include a counter suitable for counting a number of times a programmable element in the lattice detects a condition. The counter may be configured to output in response to counting the condition was detected a certain number of times. For example, the counter may be configured to output in response to determining a condition was detected at least (or no more than) the certain number of times, determining the condition was detected exactly the certain number of times, or determining the condition was detected within a certain range of times. The counter may be coupled to other counters in the device for determining high-count operations and/or certain quantifiers.

    Abstract translation: 公开了方法和装置，其中包括有限状态机格的装置。 格子可以包括适合于对格子中的可编程元件检测到条件的次数进行计数的计数器。 计数器可以配置为响应于计数而输出，条件被检测到一定次数。 例如，计数器可以被配置为响应于确定至少（或不超过）一定次数检测到的条件而输出，确定条件被精确地检测到一定次数，或者确定检测到条件 在一定的时间范围内。 计数器可以耦合到设备中的其他计数器，用于确定高计数操作和/或某些量化器。

    APPARATUS WITH REFRESH MANAGEMENT MECHANISM
    47.
    发明申请
    APPARATUS WITH REFRESH MANAGEMENT MECHANISM 有权

    公开(公告)号：US20220375509A1

    公开(公告)日：2022-11-24

    申请号：US17882894

    申请日：2022-08-08

    Applicant: Micron Technology, Inc.

    Inventor： Nathaniel J. Meier ,  James S. Rehmeyer ,  David R. Brown

    IPC: G11C11/406 ,  G11C29/52

    Abstract: Methods, apparatuses, and systems related to managing operations performed in response to refresh management (RFM) commands A controller generates the RFM command for coordinating a refresh management operation targeted for implementation at an apparatus. The apparatus tracks refresh target set that includes refresh management target locations within the apparatus. According to the tracked refresh management target set, the apparatus selectively implements the targeted refresh management operation and/or a response operation in addition to or as a replacement for the targeted refresh management operation.

    Methods and apparatuses for reducing power consumption in a pattern recognition processor
    49.
    发明授权
    Methods and apparatuses for reducing power consumption in a pattern recognition processor 有权

    公开(公告)号：US11151140B2

    公开(公告)日：2021-10-19

    申请号：US16206290

    申请日：2018-11-30

    Applicant: Micron Technology, Inc.

    Inventor： Harold B Noyes ,  David R. Brown

    IPC: G06F16/2455 ,  G06F16/903 ,  G06K9/00 ,  G06F1/3296

    Abstract: Apparatuses and methods are provided for reducing power consumption in a pattern-recognition processor. A power control circuit may be coupled to a block of programmed state machines to enable selective activation and deactivation of the block during a pattern search. The block may be deactivated if the pattern search is no longer active in that block and activated when needed by the pattern search. Additionally, the block may be deactivated based on an identifier of the data stream being searched. Excess blocks not used for any programmed state machines may be disabled such that they are not refreshed during a memory cycle.

    Shared address counters for multiple modes of operation in a memory device
    50.
    发明授权
    Shared address counters for multiple modes of operation in a memory device 有权

    公开(公告)号：US10908990B2

    公开(公告)日：2021-02-02

    申请号：US16418529

    申请日：2019-05-21

    Applicant: Micron Technology, Inc.

    Inventor： David R. Brown

    IPC: G06F11/10 ,  G06F3/06 ,  G06F12/00

    Abstract: As described above, certain modes of operation, such as the Fast Zero mode and the ECS mode, may facilitate sequential access to individual cells of a memory array. To facilitate this functionality, a command controller may be provided, including one or more individual controllers to control the address sequencing when a particular mode entry command (e.g., Fast Zero or ECS) is received. In order to generate internal addresses to be accessed sequentially, one or more counters may also be provided. Advantageously, the counters may be shared such that they can be used in any mode of operation that may require address sequencing of all or large portions of the memory array, such as the Fast Zero mode or the ECS mode.

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