公开(公告)号：US10892680B2

公开(公告)日：2021-01-12

申请号：US16808176

申请日：2020-03-03

Applicant: Micron Technology, Inc.

Inventor： Michele Piccardi ,  Xiaojiang Guo ,  Qiang Tang

IPC: H02M3/07

Abstract: An electronic device includes a reconfigurable charge pump including selectively connectable pump units for varying a generated voltage level. A control circuit may is configured to activate or deactivate the reconfigurable charge pump. The reconfigurable charge pump may track a duration based on activating the reconfigurable charge pump. When the duration exceeds a threshold, the control circuit may generates a signal according to the generated voltage level to reconfigure the electrical connections between the selectively connectable pump units.

公开(公告)号：US10891993B2

公开(公告)日：2021-01-12

申请号：US16429209

申请日：2019-06-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kaveh Shakeri ,  Ali Feiz Zarrin Ghalam ,  Qiang Tang ,  Eric N. Lee

IPC: G11C7/10 ,  G11C7/22 ,  G11C7/06 ,  G11C8/06 ,  G11C8/04 ,  G11C8/18 ,  G11C16/04

Abstract: A wave pipeline includes a first stage, a plurality of second stages, and a third stage. The first stage receives a data signal representative of data and a clock signal, and may process the data at a first data rate equal to a clock rate of the clock signal. Each second stage may process respective data in response to a respective clock cycle received from the first stage at a second data rate equal to the first data rate times the number of second stages. The third stage may process data received from each second stage at the first data rate. The first stage divides the data signal and the clock signal between the plurality of second stages. The third stage merges the respective data and the respective clock cycles from each of the plurality of second stages to provide a merged data signal and a return clock signal.

公开(公告)号：US10854301B2

公开(公告)日：2020-12-01

申请号：US16182355

申请日：2018-11-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Feng Pan ,  Ramin Ghodsi ,  Qiang Tang

IPC: G11C16/34 ,  G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/16 ,  G11C16/24

Abstract: Apparatuses and methods for reducing read disturb are described herein. An example apparatus may include a first memory subblock including a first select gate drain (SGD) switch and a first select gate source (SGS) switch, a second memory subblock including a second SGD switch and a second SGS switch, and an access line associated with the first and second memory subblocks. The apparatus may include a control unit configured to enable the first and second SGD switches and the first and second SGS switches during a first portion of a read operation and to provide a first voltage on the access line during the first portion. The control unit may be configured to disable the first SGD switch and the first SGS switches during a second portion of the read operation and to provide a second voltage on the access line during the second portion.

公开(公告)号：US10802721B2

公开(公告)日：2020-10-13

申请号：US16398646

申请日：2019-04-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Eric Lee ,  Qiang Tang ,  Ali Feiz Zarrin Ghalam ,  Hoon Choi ,  Daesik Song

IPC: G11C7/10 ,  G06F3/06 ,  G11C16/32 ,  G11C16/26 ,  G06F12/0802 ,  G11C7/22 ,  G06F12/02

Abstract: Memory device including a controller configured to cause the memory device to generate a first clock edge of a first clock signal in response to a first clock edge of a second clock signal; to generate a second, opposite, clock edge of the first clock signal immediately following the first clock edge of the first clock signal in response to a second, opposite, clock edge of the second clock signal immediately following the first clock edge of the second clock signal; and to latch data for output from the memory device in response to the second clock edge of the first clock signal.

公开(公告)号：US20190272856A1

公开(公告)日：2019-09-05

申请号：US16417528

申请日：2019-05-20

Applicant: Micron Technology, Inc.

Inventor： Xiaojiang Guo ,  Qiang Tang

IPC: G11C5/14 ,  G11C16/30

Abstract: Apparatuses and methods for mixed charge pumps with voltage regulator circuits is disclosed. An example apparatus comprises a first charge pump circuit configured to provide a first voltage, a second charge pump circuit configured to provide a second voltage, a plurality of coupling circuits configured to voltage couple and current couple the first voltage and the second voltage to a common node to provide a regulated voltage, and a feedback circuit configured to regulate the first voltage and the second voltage based on the regulated voltage.

公开(公告)号：US20190267093A1

公开(公告)日：2019-08-29

申请号：US16412627

申请日：2019-05-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Xiaojiang Guo ,  Guanglei An ,  Qiang Tang

IPC: G11C16/12 ,  G11C16/14 ,  G11C16/34 ,  G11C16/10 ,  G11C16/08 ,  G11C16/04

Abstract: Methods of operating a memory include determining a target voltage level for an access line voltage, determining a target overdrive voltage level for gating the access line voltage to an access line coupled to a plurality of memory cells, generating a voltage level for the access line voltage in response to its target voltage level and generating a voltage level for gating the access line voltage to the access line in response to the target overdrive voltage level, and applying the access line voltage to the access line while applying the voltage level for gating the access line voltage to a control gate of a string driver connected to the access line. Apparatus include a voltage regulator having variable resistance paths between a voltage signal node and an output node, and between the voltage signal node and an input of a comparator of the voltage regulator.

公开(公告)号：US20190258400A1

公开(公告)日：2019-08-22

申请号：US16398646

申请日：2019-04-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Eric Lee ,  Qiang Tang ,  Ali Feiz Zarrin Ghalam ,  Hoon Choi ,  Daesik Song

IPC: G06F3/06 ,  G11C16/26 ,  G11C16/32 ,  G11C7/10 ,  G11C7/22 ,  G06F12/0802 ,  G06F12/02

Abstract: Memory device including a controller configured to cause the memory device to generate a first clock edge of a first clock signal in response to a first clock edge of a second clock signal; to generate a second, opposite, clock edge of the first clock signal immediately following the first clock edge of the first clock signal in response to a second, opposite, clock edge of the second clock signal immediately following the first clock edge of the second clock signal; and to latch data for output from the memory device in response to the second clock edge of the first clock signal.

公开(公告)号：US10388382B2

公开(公告)日：2019-08-20

申请号：US15693133

申请日：2017-08-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Xiaojiang Guo ,  Guanglei An ,  Qiang Tang

IPC: G11C16/12 ,  G11C16/14 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/34 ,  G11C8/08

Abstract: Methods of operating a memory include determining a target voltage level for an access line voltage, determining a target overdrive voltage level for gating the access line voltage to an access line coupled to a plurality of memory cells, generating a voltage level for the access line voltage in response to its target voltage level and generating a voltage level for gating the access line voltage to the access line in response to the target overdrive voltage level, and applying the access line voltage to the access line while applying the voltage level for gating the access line voltage to a control gate of a string driver connected to the access line. Apparatus include a voltage regulator having variable resistance paths between a voltage signal node and an output node, and between the voltage signal node and an input of a comparator of the voltage regulator.

公开(公告)号：US20190214086A1

公开(公告)日：2019-07-11

申请号：US15864069

申请日：2018-01-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Qiang Tang ,  Ramin Ghodsi

IPC: G11C16/10 ,  G11C16/04 ,  H03K19/0185 ,  G11C16/26 ,  H03K19/00

Abstract: Methods of operating an integrated circuit device, and integrated circuit devices configured to perform methods, including applying a particular voltage level to a first input of an input/output (I/O) buffer and to a second input of the I/O buffer, determining whether the I/O buffer is deemed to exhibit offset, and applying an adjustment to the I/O buffer offset while applying the particular voltage level to the first input of the I/O buffer and to the second input of the I/O buffer if the I/O buffer is deemed to exhibit offset.

公开(公告)号：US20190190501A1

公开(公告)日：2019-06-20

申请号：US16204841

申请日：2018-11-29

Applicant: Micron Technology, Inc.

Inventor： Guan Wang ,  Qiang Tang ,  Ali Feiz Zarrin Ghalam

IPC: H03K3/017 ,  G06F1/10 ,  H04L25/06 ,  G11C7/22 ,  H03K5/156

Abstract: Several embodiments of electrical circuit devices and systems with clock distortion calibration circuitry are disclosed herein. In one embodiment, an electrical circuit device includes an electrical circuit die having clock distortion calibration circuitry to calibrate a clock signal. The clock distortion calibration circuitry is configured to compare a first duty cycle of a first voltage signal of the clock signal to a second duty cycle of a second voltage signal of the clock signal. Based on the comparison, the clock calibration circuitry is configured to adjust a trim value associated with at least one of the first and the second duty cycles of the first and the second voltage signals, respectively, to calibrate at least one of the first and the second duty cycles and account for duty cycle distortion encountered as the clock signal propagates through a clock tree of the electrical circuit device.