公开(公告)号：US10985165B2

公开(公告)日：2021-04-20

申请号：US16543799

申请日：2019-08-19

Applicant: Micron Technology, Inc.

Inventor： Si-Woo Lee ,  Kyuseok Lee ,  Sangmin Hwang

IPC: H01L27/108 ,  G11C5/06 ,  H01L21/768

Abstract: A method of forming a microelectronic device comprises forming a spacer structure having a rectangular ring horizontal cross-sectional shape over a transistor, a portion of the spacer structure horizontally overlapping a drain region of the transistor. A masking structure is formed over the spacer structure and the transistor, the masking structure exhibiting an opening therein horizontally overlapping the drain region of the transistor and the portion of the spacer structure. A portion of an isolation structure overlying the drain region of the transistor is removed using the masking structure and the portion of the spacer structure as etching masks to form a trench vertically extending through the isolation structure to the drain region of the transistor. A drain contact structure is formed within the trench in the isolation structure. Microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US10347322B1

公开(公告)日：2019-07-09

申请号：US15900403

申请日：2018-02-20

Applicant: Micron Technology, Inc.

Inventor： Tae H. Kim ,  Sangmin Hwang ,  Si-Woo Lee

IPC: G11C11/4091 ,  G11C11/4097 ,  G11C11/22

Abstract: Some embodiments include an apparatus having first and second comparative bitlines extending horizontally and coupled with a sense amplifier. First memory cell structures are coupled with the first comparative bitline. Each of the first memory cell structures has a first transistor associated with a first capacitor. Second memory cell structures are coupled with the second comparative bitline. Each of the second memory cell structures has a second transistor associated with a second capacitor. Each of the first capacitors has a container-shaped first node and is vertically offset from an associated first sister capacitor which is a mirror image of its associated first capacitor along a horizontal plane. Each of the second capacitors has a container-shaped first node and is vertically offset from an associated second sister capacitor which is a mirror image of its associated second capacitor along the horizontal plane.

公开(公告)号：US20190051653A1

公开(公告)日：2019-02-14

申请号：US16161381

申请日：2018-10-16

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Kamal M. Karda ,  Wolfgang Mueller ,  Sourabh Dhir ,  Robert Kerr ,  Sangmin Hwang ,  Haitao Liu

IPC: H01L27/108 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L23/528

Abstract: An array of recessed access gate lines includes active area regions having dielectric trench isolation material there-between. The trench isolation material comprises dielectric projections extending into opposing ends of individual active area regions under an elevationally outermost surface of material of the active area regions. The active area material is elevationally over the dielectric projections. Recessed access gate lines individually extend transversally across the active area regions and extend between the ends of immediately end-to-end adjacent active area regions within the dielectric trench isolation material. Other arrays are disclosed, as are methods.

公开(公告)号：US09263455B2

公开(公告)日：2016-02-16

申请号：US13948746

申请日：2013-07-23

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Kamal M. Karda ,  Wolfgang Mueller ,  Sourabh Dhir ,  Robert Kerr ,  Sangmin Hwang ,  Haitao Liu

IPC: H01L27/108 ,  H01L21/762 ,  H01L29/66

CPC classification number: H01L27/10823 ,  H01L21/76232 ,  H01L23/528 ,  H01L27/10808 ,  H01L27/10876 ,  H01L29/0649 ,  H01L29/66621 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An array of recessed access gate lines includes active area regions having dielectric trench isolation material there-between. The trench isolation material comprises dielectric projections extending into opposing ends of individual active area regions under an elevationally outermost surface of material of the active area regions. The active area material is elevationally over the dielectric projections. Recessed access gate lines individually extend transversally across the active area regions and extend between the ends of immediately end-to-end adjacent active area regions within the dielectric trench isolation material. Other arrays are disclosed, as are methods.

Abstract translation: 一组凹进的存取栅极线包括其间具有介电沟槽隔离材料的有源区域区域。 沟槽隔离材料包括延伸到有源区域区域的材料的最外表面下方的各个有源区域的相对端的电介质突起。 有源区域材料在电介质突起上是垂直的。 嵌入式栅极线分别横跨有源区域区域延伸并且在电介质沟槽隔离材料内的紧邻端到端相邻有源区域区域的端部之间延伸。 公开了其他阵列，方法也是如此。

公开(公告)号：US20140313810A1

公开(公告)日：2014-10-23

申请号：US13866693

申请日：2013-04-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sangmin Hwang ,  Tae H. Kim ,  Hoyoung Kang

IPC: G11C11/401 ,  G11C11/408

CPC classification number: G11C11/408 ,  G11C7/18 ,  G11C11/4097

Abstract: A memory array includes segmented global and local digit lines in which the global digit line segments are switchably coupled to one of a plurality of local digit line segments at a time. A sense circuit coupled to a global digit line segment can be switched to sense memory cells coupled to one of the plurality of local digit lines at a first time and memory cells coupled to a second one of the plurality of local digit lines at a second time. Neither the global digit line segments nor the local digit line segments extend through the entire memory array.

Abstract translation: 存储器阵列包括分段的全局和局部数字线，其中全局数字线段一次可切换地耦合到多个局部数字线段之一。 耦合到全局数字线段的感测电路可以被切换以感测在第一时间耦合到多个本地数字线中的一个的存储器单元，并且在第二时间耦合到多个本地数字线中的第二个的存储器单元 。 全局数字线段和本地数字线段都不会延伸穿过整个存储器阵列。