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41.发明授权公开(公告)号：US06836159B2
公开(公告)日：2004-12-28
申请号：US10248968
申请日：2003-03-06
IPC分类号： H03K300
CPC分类号： H03K17/102 , H03K17/6874
摘要： An integrated high-voltage switching circuit includes a switch having ON and OFF states and having a parasitic gate capacitance. The switch consists of a pair of DMOS transistors integrated back to back and having a shared gate terminal, the drains of the DMOS transistors being connected to the input and output terminals of the switch respectively. The switching circuit further includes a turn-on circuit comprising a PMOS transistor having its drain connected to the shared gate terminal of the switch via a first diode, having its source connected to a global switch gate bias voltage terminal from which the PMOS transistor draws current, and having its gate electrically coupled to a switch gate control terminal that receives a switch gate control voltage input. The switch transitions from the OFF state to the ON state in response to a first transition of the switch gate control voltage input that causes the PMOS transistor to turn on, and the switch remains in the ON state in response to a second transition of the switch gate control voltage input that causes the PMOS transistor to turn off. The DMOS transistors turn on in response to the shared gate being coupled to the switch gate bias voltage when the PMOS transistor turns on.
摘要翻译： 集成的高压开关电路包括具有ON和OFF状态并具有寄生栅极电容的开关。 开关由一对背对背集成的DMOS晶体管组成，具有共用栅极端子，DMOS晶体管的漏极分别连接到开关的输入和输出端子。 开关电路还包括导通电路，其包括PMOS晶体管，其PMOS的漏极经由第一二极管连接到开关的共享栅极端子，其源极连接到全局开关栅极偏置电压端子，PMOS晶体管从该栅极偏置电压端子吸取电流 并且其栅极电耦合到接收开关栅极控制电压输入的开关栅极控制端子。 响应于导致PMOS晶体管导通的开关栅极控制电压输入的第一跃迁，开关从OFF状态转变到ON状态，并且开关响应于开关的第二过渡而保持在ON状态 栅极控制电压输入使PMOS晶体管关断。 当PMOS晶体管导通时，DMOS晶体管响应于共享栅极耦合到开关栅极偏置电压而导通。
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公开(公告)号：US06246275B1
公开(公告)日：2001-06-12
申请号：US09441323
申请日：1999-11-16
IPC分类号： H03K300
摘要： The present invention provides a clocked comparator which extends the time period before an input signal is measured to include most of the clock cycle, thereby increasing the amount of time available for the input signal to achieve a “steady-state” condition. After the input signal achieves a “steady-state” condition the comparator compares the input signal against a reference voltage and a decision register latches the comparator output. The decision signal may then be further latched to be made available for external circuitry in the subsequent clock cycle. A multi-phase programmable signal generator is connected to the clocked generator for generating a plurality of timing signals. The multi-phase programmable signal generator employs a plurality of single bit registers interconnected in series to form a shift register. Output signals generated by the programmable signal generator are used to drive the switches and register clocks of the clocked comparator.
摘要翻译： 本发明提供了一种时钟比较器，其延长了在测量输入信号之前的时间段以包括大部分时钟周期，从而增加了可用于输入信号以实现“稳态”状态的时间量。 在输入信号达到“稳态”状态之后，比较器将输入信号与参考电压进行比较，并且决定寄存器锁存比较器输出。 然后可以进一步锁定该决定信号以在随后的时钟周期内使外部电路可用。 多相可编程信号发生器连接到时钟发生器，用于产生多个定时信号。 多相可编程信号发生器采用串联互连的多个单位寄存器来形成移位寄存器。 由可编程信号发生器产生的输出信号用于驱动定时比较器的开关和寄存器时钟。
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43.发明授权Apparatus and method for a high frequency clocked comparator and apparatus for multi-phase programmable clock generator 失效一种用于多相可编程时钟发生器的高频时钟比较器和装置的装置和方法
公开(公告)号：US6037809A
公开(公告)日：2000-03-14
申请号：US89604
申请日：1998-06-02
摘要： The present invention provides a clocked comparator which extends the time period before an input signal is measured to include most of the clock cycle, thereby increasing the amount of time available for the input signal to achieve a "steady-state" condition. After the input signal achieves a "steady-state" condition the comparator compares the input signal against a reference voltage and a decision register latches the comparator output. The decision signal may then be further latched to be made available for external circuitry in the subsequent clock cycle. A multi-phase programmable signal generator is connected to the clocked generator for generating a plurality of timing signals. The multi-phase programmable signal generator employs a plurality of single bit registers interconnected in series to form a shift register. Output signals generated by the programmable signal generator are used to drive the switches and register clocks of the clocked comparator.
摘要翻译： 本发明提供了一种时钟比较器，其延长了在测量输入信号之前的时间段以包括大部分时钟周期，从而增加了可用于输入信号以实现“稳态”状态的时间量。 在输入信号达到“稳态”状态之后，比较器将输入信号与参考电压进行比较，并且决定寄存器锁存比较器输出。 然后可以进一步锁定该决定信号以在随后的时钟周期内使外部电路可用。 多相可编程信号发生器连接到时钟发生器，用于产生多个定时信号。 多相可编程信号发生器采用串联互连的多个单位寄存器来形成移位寄存器。 由可编程信号发生器产生的输出信号用于驱动时钟控制比较器的开关和寄存器时钟。
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公开(公告)号：US08176787B2
公开(公告)日：2012-05-15
申请号：US12337328
申请日：2008-12-17
CPC分类号： A61B8/00 , A61B8/4281 , A61B8/4483 , G01S15/8925
摘要： According to embodiments of the present technique, a system and a method for addressing transducers in a two-dimensional transducer array is disclosed. According to one aspect of the present technique, the transducers are arranged in rows and columns, and the columns are coupled to a shared transmit and receive circuitry while the rows are coupled to a row selection circuitry. In another embodiment, each transducer is coupled to a separate, dedicated transmit circuitry and the columns are coupled to a shared receive circuitry.
摘要翻译： 根据本技术的实施例，公开了一种用于寻址二维换能器阵列中的换能器的系统和方法。 根据本技术的一个方面，换能器以行和列布置，并且列被耦合到共享的发送和接收电路，而行被耦合到行选择电路。 在另一个实施例中，每个换能器耦合到单独的专用发射电路，并且列耦合到共享接收电路。
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45.发明申请公开(公告)号：US20110071397A1
公开(公告)日：2011-03-24
申请号：US12714239
申请日：2010-02-26
申请人： Robert Gideon Wodnicki , Rayette Ann Fisher , Charles Gerard Woychik , Shubhra Bansal , Albert Taesung Byun
发明人： Robert Gideon Wodnicki , Rayette Ann Fisher , Charles Gerard Woychik , Shubhra Bansal , Albert Taesung Byun
CPC分类号： B23K1/0016 , B06B1/0629
摘要： A modular and tileable sensor array with routing in the interposer carrying the signals from the sensors to the integrated circuits. In one embodiment a large area modular sensor array assembly includes one or more tileable modules coupled together. The tileable modules have a plurality of transducer cells forming a sensor, an interposer coupled on a first side to the plurality of transducer cells by a plurality, one or more integrated circuits coupled to a second side of the interposer, wherein the interposer is configured to form the connection of at least some of the transducer cells to the integrated circuits, and one or more input/output connectors coupled to the interposer and providing an external interface.
摘要翻译： 一种模块化且可分散的传感器阵列，其具有在插入器中的路由，其将来自传感器的信号传送到集成电路。 在一个实施例中，大面积模块化传感器阵列组件包括耦合在一起的一个或多个可瓦片模块。 可拼接模块具有形成传感器的多个换能器单元，通过耦合到中介层的第二侧的多个一个或多个集成电路在第一侧耦合到多个换能器单元的插入件，其中插入件配置成 形成至少一些传感器单元与集成电路的连接，以及耦合到插入器并提供外部接口的一个或多个输入/输出连接器。
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公开(公告)号：US07781238B2
公开(公告)日：2010-08-24
申请号：US11951360
申请日：2007-12-06
申请人： Robert Gideon Wodnicki , Stacey Joy Kennerly , Wei-Cheng Tian , Kevin Matthew Durocher , David Martin Mills , Charles Gerard Woychik , Lowell Scott Smith
发明人： Robert Gideon Wodnicki , Stacey Joy Kennerly , Wei-Cheng Tian , Kevin Matthew Durocher , David Martin Mills , Charles Gerard Woychik , Lowell Scott Smith
IPC分类号： H01L21/66
摘要： A method for making a testable sensor assembly is provided. The method includes forming a first sensor array on a first substrate having a first side and a second side, wherein the first sensor array is formed on the first side of the first substrate, coupling a first semiconductor wafer having a first side and a second side to the first sensor array, wherein the first side of the first semiconductor wafer is coupled to the first sensor array, thinning one of the second side of the first substrate or the second side of the first semiconductor wafer, and testing the first sensor array to identify operational and non-operational units in the testable sensor assembly before integration of the sensor assembly with interface electronics.
摘要翻译： 提供了制造可测试的传感器组件的方法。 该方法包括在具有第一侧和第二侧的第一衬底上形成第一传感器阵列，其中第一传感器阵列形成在第一衬底的第一侧上，将具有第一侧和第二侧的第一半导体晶片 到第一传感器阵列，其中第一半导体晶片的第一侧耦合到第一传感器阵列，使第一衬底的第二侧或第一半导体晶片的第二面之一变薄，并将第一传感器阵列测试为 在将传感器组件与接口电子器件集成之前，确定可测试传感器组件中的操作和非操作单元。
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47.发明授权Transmit and receive interface array for highly integrated ultrasound scanner 有权发射和接收接口阵列，用于高度集成的超声波扫描仪公开(公告)号：US07775979B2
公开(公告)日：2010-08-17
申请号：US11172599
申请日：2005-06-29
IPC分类号： A61B8/00
CPC分类号： G10K11/341 , A61B8/56 , G01S7/5208
摘要： An ultrasonic transducer probe having a highly integrated interface circuit array. Low-voltage transmit control signals from the system are transmitted on the system transmit channels via the ultrasound probe cable and into the interface circuit array. These transmit control signals are routed through the interface circuit array using a dense switching matrix. Once the low-voltage transmit control signals reach individual cells within the interface array, they are decoded and used to control local high-voltage pulser circuits to drive individual ultrasound transducer elements made up of selected subelements that are co-integrated with the interface electronics. The interface cell circuitry further comprises a high-voltage transmit/receive switch, which is closed when the high-voltage pulser is transmitting to protect the low-voltage components.
摘要翻译： 具有高度集成的接口电路阵列的超声换能器探针。 来自系统的低电压发射控制信号通过超声探头电缆在系统发射通道上传输到接口电路阵列中。 这些发送控制信号使用密集的交换矩阵通过接口电路阵列路由。 一旦低压发射控制信号到达接口阵列内的单个小区，就将它们解码并用于控制本地高压脉冲发生器电路，以驱动由与接口电子器件共同集成的选定子元件组成的各个超声换能器元件。 接口单元电路还包括高压发射/接收开关，当高压脉冲发生器正在传输时，该高压发射/接收开关闭合以保护低电压部件。
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公开(公告)号：US20090148967A1
公开(公告)日：2009-06-11
申请号：US11951360
申请日：2007-12-06
申请人： Robert Gideon Wodnicki , Stacey Joy Kennerly , Wei-Cheng Tian , Kevin Matthew Durocher , David Martin Mills , Charles Gerard Woychik , Lowell Scott Smith
发明人： Robert Gideon Wodnicki , Stacey Joy Kennerly , Wei-Cheng Tian , Kevin Matthew Durocher , David Martin Mills , Charles Gerard Woychik , Lowell Scott Smith
IPC分类号： H01L21/66
摘要： A method for making a testable sensor assembly is provided. The method includes forming a first sensor array on a first substrate having a first side and a second side, wherein the first sensor array is formed on the first side of the first substrate, coupling a first semiconductor wafer having a first side and a second side to the first sensor array, wherein the first side of the first semiconductor wafer is coupled to the first sensor array, thinning one of the second side of the first substrate or the second side of the first semiconductor wafer, and testing the first sensor array to identify operational and non-operational units in the testable sensor assembly before integration of the sensor assembly with interface electronics.
摘要翻译： 提供了制造可测试的传感器组件的方法。 该方法包括在具有第一侧和第二侧的第一衬底上形成第一传感器阵列，其中第一传感器阵列形成在第一衬底的第一侧上，将具有第一侧和第二侧的第一半导体晶片 到第一传感器阵列，其中第一半导体晶片的第一侧耦合到第一传感器阵列，使第一衬底的第二侧或第一半导体晶片的第二面之一变薄，并将第一传感器阵列测试为 在将传感器组件与接口电子器件集成之前，确定可测试传感器组件中的操作和非操作单元。
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49.发明申请公开(公告)号：US20080296708A1
公开(公告)日：2008-12-04
申请号：US11809165
申请日：2007-05-31
申请人： Robert Gideon Wodnicki , Wei-Cheng Tian , Kevin Matthew Durocher , Charles Gerard Woychik , Rayette Ann Fisher , Stacey Joy Kennerly , Lowell Scott Smith , Douglas Glenn Wildes
发明人： Robert Gideon Wodnicki , Wei-Cheng Tian , Kevin Matthew Durocher , Charles Gerard Woychik , Rayette Ann Fisher , Stacey Joy Kennerly , Lowell Scott Smith , Douglas Glenn Wildes
CPC分类号： G01N29/2406 , B06B1/0292 , G01N2291/106 , H01L2224/04105 , H01L2224/24 , H01L2224/73267 , H01L2224/82
摘要： The present invention relates to a method for making an integrated sensor comprising providing a sensor array fabricated on a top surface of a bulk silicon wafer having a top surface and a bottom surface, and comprising a plurality of sensors fabricated on the top surface of the bulk silicon wafer. The method further comprises coupling an SOI wafer to the top surface of the bulk silicon wafer, thinning the back surface of the bulk silicon wafer, coupling a plurality of integrated circuit die to the back surface of the bulk silicon wafer, and removing the SOI wafer from the top surface of the bulk silicon wafer.
摘要翻译： 本发明涉及一种用于制造集成传感器的方法，其包括提供制造在具有顶表面和底表面的体硅晶片的顶表面上的传感器阵列，并且包括在本体的顶表面上制造的多个传感器 硅晶片。 该方法还包括将SOI晶片耦合到体硅晶片的顶表面，使体硅晶片的背表面变薄，将多个集成电路管芯耦合到体硅晶片的背面，以及去除SOI晶片 从体硅晶片的顶表面。
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公开(公告)号：US20080262357A1
公开(公告)日：2008-10-23
申请号：US11737414
申请日：2007-04-19
IPC分类号： A61B8/00
CPC分类号： G01S7/52017 , Y10T307/74 , Y10T307/858
摘要： A transceiver for use in an ultrasound system is provided. The transceiver is configured to operate in a transmit mode and a receive mode. The transceiver comprises a high voltage switch, a low voltage switch and a resistor coupled to the high voltage switch and the low voltage switch.
摘要翻译： 提供了一种用于超声系统的收发器。 收发器被配置为在发送模式和接收模式下操作。 收发器包括高压开关，低压开关和耦合到高压开关和低压开关的电阻器。
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