公开(公告)号：US07781238B2

公开(公告)日：2010-08-24

申请号：US11951360

申请日：2007-12-06

申请人： Robert Gideon Wodnicki ,  Stacey Joy Kennerly ,  Wei-Cheng Tian ,  Kevin Matthew Durocher ,  David Martin Mills ,  Charles Gerard Woychik ,  Lowell Scott Smith

发明人： Robert Gideon Wodnicki ,  Stacey Joy Kennerly ,  Wei-Cheng Tian ,  Kevin Matthew Durocher ,  David Martin Mills ,  Charles Gerard Woychik ,  Lowell Scott Smith

IPC分类号： H01L21/66

CPC分类号： H01L22/20 ,  H01L22/14

摘要： A method for making a testable sensor assembly is provided. The method includes forming a first sensor array on a first substrate having a first side and a second side, wherein the first sensor array is formed on the first side of the first substrate, coupling a first semiconductor wafer having a first side and a second side to the first sensor array, wherein the first side of the first semiconductor wafer is coupled to the first sensor array, thinning one of the second side of the first substrate or the second side of the first semiconductor wafer, and testing the first sensor array to identify operational and non-operational units in the testable sensor assembly before integration of the sensor assembly with interface electronics.

摘要翻译： 提供了制造可测试的传感器组件的方法。 该方法包括在具有第一侧和第二侧的第一衬底上形成第一传感器阵列，其中第一传感器阵列形成在第一衬底的第一侧上，将具有第一侧和第二侧的第一半导体晶片 到第一传感器阵列，其中第一半导体晶片的第一侧耦合到第一传感器阵列，使第一衬底的第二侧或第一半导体晶片的第二面之一变薄，并将第一传感器阵列测试为 在将传感器组件与接口电子器件集成之前，确定可测试传感器组件中的操作和非操作单元。

公开(公告)号：US20090148967A1

公开(公告)日：2009-06-11

申请号：US11951360

申请日：2007-12-06

申请人： Robert Gideon Wodnicki ,  Stacey Joy Kennerly ,  Wei-Cheng Tian ,  Kevin Matthew Durocher ,  David Martin Mills ,  Charles Gerard Woychik ,  Lowell Scott Smith

发明人： Robert Gideon Wodnicki ,  Stacey Joy Kennerly ,  Wei-Cheng Tian ,  Kevin Matthew Durocher ,  David Martin Mills ,  Charles Gerard Woychik ,  Lowell Scott Smith

IPC分类号： H01L21/66

CPC分类号： H01L22/20 ,  H01L22/14

摘要： A method for making a testable sensor assembly is provided. The method includes forming a first sensor array on a first substrate having a first side and a second side, wherein the first sensor array is formed on the first side of the first substrate, coupling a first semiconductor wafer having a first side and a second side to the first sensor array, wherein the first side of the first semiconductor wafer is coupled to the first sensor array, thinning one of the second side of the first substrate or the second side of the first semiconductor wafer, and testing the first sensor array to identify operational and non-operational units in the testable sensor assembly before integration of the sensor assembly with interface electronics.

摘要翻译： 提供了制造可测试的传感器组件的方法。 该方法包括在具有第一侧和第二侧的第一衬底上形成第一传感器阵列，其中第一传感器阵列形成在第一衬底的第一侧上，将具有第一侧和第二侧的第一半导体晶片 到第一传感器阵列，其中第一半导体晶片的第一侧耦合到第一传感器阵列，使第一衬底的第二侧或第一半导体晶片的第二面之一变薄，并将第一传感器阵列测试为 在将传感器组件与接口电子器件集成之前，确定可测试传感器组件中的操作和非操作单元。

公开(公告)号：US20080296708A1

公开(公告)日：2008-12-04

申请号：US11809165

申请日：2007-05-31

申请人： Robert Gideon Wodnicki ,  Wei-Cheng Tian ,  Kevin Matthew Durocher ,  Charles Gerard Woychik ,  Rayette Ann Fisher ,  Stacey Joy Kennerly ,  Lowell Scott Smith ,  Douglas Glenn Wildes

发明人： Robert Gideon Wodnicki ,  Wei-Cheng Tian ,  Kevin Matthew Durocher ,  Charles Gerard Woychik ,  Rayette Ann Fisher ,  Stacey Joy Kennerly ,  Lowell Scott Smith ,  Douglas Glenn Wildes

IPC分类号： H01L21/50 ,  H01L23/00

CPC分类号： G01N29/2406 ,  B06B1/0292 ,  G01N2291/106 ,  H01L2224/04105 ,  H01L2224/24 ,  H01L2224/73267 ,  H01L2224/82

摘要： The present invention relates to a method for making an integrated sensor comprising providing a sensor array fabricated on a top surface of a bulk silicon wafer having a top surface and a bottom surface, and comprising a plurality of sensors fabricated on the top surface of the bulk silicon wafer. The method further comprises coupling an SOI wafer to the top surface of the bulk silicon wafer, thinning the back surface of the bulk silicon wafer, coupling a plurality of integrated circuit die to the back surface of the bulk silicon wafer, and removing the SOI wafer from the top surface of the bulk silicon wafer.

摘要翻译： 本发明涉及一种用于制造集成传感器的方法，其包括提供制造在具有顶表面和底表面的体硅晶片的顶表面上的传感器阵列，并且包括在本体的顶表面上制造的多个传感器 硅晶片。 该方法还包括将SOI晶片耦合到体硅晶片的顶表面，使体硅晶片的背表面变薄，将多个集成电路管芯耦合到体硅晶片的背面，以及去除SOI晶片 从体硅晶片的顶表面。

公开(公告)号：US08742646B2

公开(公告)日：2014-06-03

申请号：US13433422

申请日：2012-03-29

申请人： Robert Gideon Wodnicki ,  Charles Edward Baumgartner ,  David Martin Mills ,  Kevin Matthew Durocher ,  William Hullinger Huber ,  George Charles Sogoian ,  Christopher James Kapusta

发明人： Robert Gideon Wodnicki ,  Charles Edward Baumgartner ,  David Martin Mills ,  Kevin Matthew Durocher ,  William Hullinger Huber ,  George Charles Sogoian ,  Christopher James Kapusta

IPC分类号： H01L41/08 ,  B06B1/06

CPC分类号： B06B1/0622 ,  H01L41/338 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/1433 ,  H01L2924/15321 ,  Y10T29/42 ,  H01L2924/00

摘要： An ultrasound acoustic assembly includes a number of ultrasound acoustic arrays, each array comprising an acoustic stack comprising a piezoelectric layer assembled with at least one acoustic impedance dematching layer and with a support layer. The acoustic stack defines a number of dicing kerfs and a number of acoustic elements, such that the dicing kerfs are formed between neighboring ones of the acoustic elements. The dicing kerfs extend through the piezoelectric layer and through the acoustic impedance dematching layer(s) but extend only partially through the support layer. The ultrasound acoustic assembly further includes a number of application specific integrated circuit (ASIC) die. Each ultrasound acoustic array is coupled to a respective ASIC die to form a respective acoustic-electric transducer module. Methods of manufacture are also provided.

摘要翻译： 超声波声学组件包括多个超声波阵列，每个阵列包括声叠层，声堆叠包括与至少一个声阻抗分配层和支撑层组装的压电层。 声学堆叠限定了多个切割切口和多个声学元件，使得切割切口形成在相邻的声学元件之间。 切割切口延伸穿过压电层并通过声阻抗分层，但仅部分延伸穿过支撑层。 超声波组件还包括许多专用集成电路（ASIC）芯片。 每个超声波阵列耦合到相应的ASIC管芯，以形成相应的声电传感器模块。 还提供了制造方法。

公开(公告)号：US20130257224A1

公开(公告)日：2013-10-03

申请号：US13433422

申请日：2012-03-29

申请人： Robert Gideon Wodnicki ,  Charles Edward Baumgartner ,  David Martin Mills ,  Kevin Matthew Durocher ,  William Hullinger Huber ,  George Charles Sogoian ,  Christopher James Kapusta

发明人： Robert Gideon Wodnicki ,  Charles Edward Baumgartner ,  David Martin Mills ,  Kevin Matthew Durocher ,  William Hullinger Huber ,  George Charles Sogoian ,  Christopher James Kapusta

IPC分类号： H01L41/04 ,  H01L41/113 ,  H01L41/22 ,  H01L41/047

CPC分类号： B06B1/0622 ,  H01L41/338 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/1433 ,  H01L2924/15321 ,  Y10T29/42 ,  H01L2924/00

摘要： An ultrasound acoustic assembly includes a number of ultrasound acoustic arrays, each array comprising an acoustic stack comprising a piezoelectric layer assembled with at least one acoustic impedance dematching layer and with a support layer. The acoustic stack defines a number of dicing kerfs and a number of acoustic elements, such that the dicing kerfs are formed between neighboring ones of the acoustic elements. The dicing kerfs extend through the piezoelectric layer and through the acoustic impedance dematching layer(s) but extend only partially through the support layer. The ultrasound acoustic assembly further includes a number of application specific integrated circuit (ASIC) die. Each ultrasound acoustic array is coupled to a respective ASIC die to form a respective acoustic-electric transducer module. Methods of manufacture are also provided.

摘要翻译： 超声波声学组件包括多个超声波阵列，每个阵列包括声叠层，声堆叠包括与至少一个声阻抗分配层和支撑层组装的压电层。 声学堆叠限定了多个切割切口和多个声学元件，使得切割切口形成在相邻的声学元件之间。 切割切口延伸穿过压电层并通过声阻抗分层，但仅部分延伸穿过支撑层。 超声波组件还包括许多专用集成电路（ASIC）芯片。 每个超声波阵列耦合到相应的ASIC管芯，以形成相应的声电传感器模块。 还提供了制造方法。

公开(公告)号：US20090028491A1

公开(公告)日：2009-01-29

申请号：US11828550

申请日：2007-07-26

申请人： Raymond Albert Fillion ,  Kevin Matthew Durocher ,  Richard Joseph Saia ,  Charles Gerard Woychik

发明人： Raymond Albert Fillion ,  Kevin Matthew Durocher ,  Richard Joseph Saia ,  Charles Gerard Woychik

IPC分类号： G02B6/12 ,  H01L23/48

CPC分类号： H01L23/13 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/18 ,  H01L2224/76155 ,  H01L2224/82102 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15312 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/00

摘要： An interconnect structure includes an insulative web having a first surface and a second surface; a logic device secured to the second surface of the insulative web; a frame panel assembly including a frame base having a first surface and a second surface, a first frame insulative layer disposed between the frame base first surface and the insulative web second surface, an aperture extending through the frame base and first frame insulative layer, wherein at least a portion of the logic device is disposed within the aperture, and a first frame connector disposed between a first electrically conductive layer located on the frame base first surface, and a second electrically conductive layer located on a surface of the first frame insulative layer; a device connector disposed between an I/O contact on a surface of the logic device and a third electrical conductor located on a surface of the insulative web; and an insulative layer connector that is disposed between the third electrical conductor located on a surface of the insulative web and the second electrically conductive layer located on a surface of the first frame insulative layer.

摘要翻译： 互连结构包括具有第一表面和第二表面的绝缘网; 固定在绝缘网的第二表面上的逻辑装置; 框架面板组件，包括具有第一表面和第二表面的框架基座，设置在框架基部第一表面和绝缘网片第二表面之间的第一框架绝缘层，延伸穿过框架基部和第一框架绝缘层的孔，其中 所述逻辑器件的至少一部分设置在所述孔内，并且设置在位于所述框架基底第一表面上的第一导电层之间的第一框架连接器和位于所述第一框架绝缘层的表面上的第二导电层 ; 设置在所述逻辑器件的表面上的I / O触点和位于所述绝缘网的表面上的第三电导体之间的器件连接器; 以及绝缘层连接器，其设置在位于所述绝缘片的表面上的所述第三电导体和位于所述第一框架绝缘层的表面上的所述第二导电层之间。

公开(公告)号：US08498131B2

公开(公告)日：2013-07-30

申请号：US13136736

申请日：2011-08-09

申请人： Raymond Albert Fillion ,  Kevin Matthew Durocher ,  Richard Joseph Saia ,  Charles Gerard Woychik

发明人： Raymond Albert Fillion ,  Kevin Matthew Durocher ,  Richard Joseph Saia ,  Charles Gerard Woychik

IPC分类号： H05K7/00

CPC分类号： H01L23/13 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/18 ,  H01L2224/76155 ,  H01L2224/82102 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15312 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/00

摘要： An interconnect structure includes an insulative web having a first surface and a second surface; a logic device secured to the second surface of the insulative web; a frame panel assembly including a frame base having a first surface and a second surface, a first frame insulative layer disposed between the frame base first surface and the insulative web second surface, an aperture extending through the frame base and first frame insulative layer, wherein at least a portion of the logic device is disposed within the aperture, and a first frame connector disposed between a first electrically conductive layer located on the frame base first surface, and a second electrically conductive layer located on a surface of the first frame insulative layer; a device connector disposed between an I/O contact on a surface of the logic device and a third electrical conductor located on a surface of the insulative web; and an insulative layer connector that is disposed between the third electrical conductor located on a surface of the insulative web and the second electrically conductive layer located on a surface of the first frame insulative layer.

摘要翻译： 互连结构包括具有第一表面和第二表面的绝缘网; 固定在绝缘网的第二表面上的逻辑装置; 框架面板组件，包括具有第一表面和第二表面的框架基座，设置在框架基部第一表面和绝缘网片第二表面之间的第一框架绝缘层，延伸穿过框架基部和第一框架绝缘层的孔，其中 所述逻辑器件的至少一部分设置在所述孔内，并且设置在位于所述框架基底第一表面上的第一导电层之间的第一框架连接器和位于所述第一框架绝缘层的表面上的第二导电层 ; 设置在所述逻辑器件的表面上的I / O触点和位于所述绝缘网的表面上的第三电导体之间的器件连接器; 以及绝缘层连接器，其设置在位于所述绝缘片的表面上的所述第三电导体和位于所述第一框架绝缘层的表面上的所述第二导电层之间。

公开(公告)号：US20110299821A1

公开(公告)日：2011-12-08

申请号：US13136736

申请日：2011-08-09

申请人： Raymond Albert Fillion ,  Kevin Matthew Durocher ,  Richard Joseph Saia ,  Charles Gerard Woychik

发明人： Raymond Albert Fillion ,  Kevin Matthew Durocher ,  Richard Joseph Saia ,  Charles Gerard Woychik

IPC分类号： G02B6/00 ,  H05K5/00

CPC分类号： H01L23/13 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/18 ,  H01L2224/76155 ,  H01L2224/82102 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15312 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/00

摘要： An interconnect structure includes an insulative web having a first surface and a second surface; a logic device secured to the second surface of the insulative web; a frame panel assembly including a frame base having a first surface and a second surface, a first frame insulative layer disposed between the frame base first surface and the insulative web second surface, an aperture extending through the frame base and first frame insulative layer, wherein at least a portion of the logic device is disposed within the aperture, and a first frame connector disposed between a first electrically conductive layer located on the frame base first surface, and a second electrically conductive layer located on a surface of the first frame insulative layer; a device connector disposed between an I/O contact on a surface of the logic device and a third electrical conductor located on a surface of the insulative web; and an insulative layer connector that is disposed between the third electrical conductor located on a surface of the insulative web and the second electrically conductive layer located on a surface of the first frame insulative layer.

摘要翻译： 互连结构包括具有第一表面和第二表面的绝缘网; 固定在绝缘网的第二表面上的逻辑装置; 框架面板组件，包括具有第一表面和第二表面的框架基座，设置在框架基部第一表面和绝缘网片第二表面之间的第一框架绝缘层，延伸穿过框架基部和第一框架绝缘层的孔，其中 所述逻辑装置的至少一部分设置在所述孔内，并且设置在位于所述框架基底第一表面上的第一导电层之间的第一框架连接器和位于所述第一框架绝缘层的表面上的第二导电层 ; 设置在所述逻辑器件的表面上的I / O触点和位于所述绝缘网的表面上的第三电导体之间的器件连接器; 以及绝缘层连接器，其设置在位于所述绝缘片的表面上的所述第三电导体和位于所述第一框架绝缘层的表面上的所述第二导电层之间。

公开(公告)号：US08824635B2

公开(公告)日：2014-09-02

申请号：US13283373

申请日：2011-10-27

申请人： John Eric Tkaczyk ,  Kevin Matthew Durocher ,  James Rose ,  Haochuan Jiang ,  Abdelaziz Ikhlef ,  Vladimir Lobastov ,  Daniel David Harrison

发明人： John Eric Tkaczyk ,  Kevin Matthew Durocher ,  James Rose ,  Haochuan Jiang ,  Abdelaziz Ikhlef ,  Vladimir Lobastov ,  Daniel David Harrison

IPC分类号： H05G1/64 ,  H01L27/148 ,  G01T1/16 ,  G01T1/208

CPC分类号： G01T1/247 ,  A61B6/037 ,  A61B6/4233 ,  G01N2223/419 ,  G01N2223/507 ,  G01T1/249 ,  G01T7/005

摘要： Detector modules for an imaging system and methods of manufacturing are provided. One detector module includes a substrate, a direct conversion sensor material coupled to the substrate and a flexible interconnect electrically coupled to the direct conversion sensor material and configured to provide readout of electrical signals generated by the direct conversion sensor material. The detector module also includes at least one illumination source for illuminating the direct conversion sensor material.

摘要翻译： 提供了用于成像系统的检测器模块和制造方法。 一个检测器模块包括衬底，耦合到衬底的直接转换传感器材料和电耦合到直接转换传感器材料并被配置为提供由直接转换传感器材料产生的电信号的读出的柔性互连。 检测器模块还包括用于照亮直接转换传感器材料的至少一个照明源。

公开(公告)号：US08405996B2

公开(公告)日：2013-03-26

申请号：US12826337

申请日：2010-06-29

申请人： David Mulford Shaddock ,  Deng Tao ,  Hendrik Pieter Jacobus De Bock ,  Dalong Zhong ,  Christopher Michael Eastman ,  Kevin Matthew Durocher ,  Stanton Earl Weaver, Jr.

发明人： David Mulford Shaddock ,  Deng Tao ,  Hendrik Pieter Jacobus De Bock ,  Dalong Zhong ,  Christopher Michael Eastman ,  Kevin Matthew Durocher ,  Stanton Earl Weaver, Jr.

IPC分类号： H05K7/20

CPC分类号： H01L23/433 ,  B82Y30/00 ,  B82Y40/00 ,  C25D5/022 ,  C25D7/12 ,  F28F2013/006 ,  F28F2255/00 ,  H01L2924/0002 ,  Y10T29/49 ,  Y10T428/30 ,  H01L2924/00

摘要： An article and method of forming the article is disclosed. The article includes a heat source, a heat-sink, and a thermal interface element having a plurality of freestanding nanosprings, a top layer, and a bottom layer. The nanosprings, top layer, and the bottom layers of the article include at least one inorganic material. The article can be prepared using a number of methods including the methods such as GLAD and electrochemical deposition.

摘要翻译： 公开了一种形成物品的制品和方法。 该制品包括热源，散热器和具有多个独立纳米脉冲，顶层和底层的热界面元件。 制品的纳米螺旋，顶层和底层包括至少一种无机材料。 该制品可以使用许多方法制备，包括诸如GLAD和电化学沉积的方法。