公开(公告)号：US20050191980A1

公开(公告)日：2005-09-01

申请号：US10788588

申请日：2004-02-27

申请人： Omid Oliaei

发明人： Omid Oliaei

IPC分类号： H03H11/26 ,  H03M3/00 ,  H03M3/02 ,  H04B1/16

CPC分类号： H03M3/40 ,  H03M3/418

摘要： A complex cascade sigma-delta modulator for analog-to-digital conversion applications. The modulator includes first and second sigma-delta modulator stages, combined with a complex digital noise cancellation circuit. In addition, analog-to-digital conversion of baseband signals using a complex sigma-delta modulator is also presented.

摘要翻译： 用于模数转换应用的复杂级联Σ-Δ调制器。 该调制器包括与复数数字噪声消除电路组合的第一和第二Σ-Δ调制器级。 此外，还提出了使用复数Σ-Δ调制器的基带信号的模数转换。

公开(公告)号：US20050052299A1

公开(公告)日：2005-03-10

申请号：US10381075

申请日：2003-03-18

申请人： Omid Oliaei

发明人： Omid Oliaei

IPC分类号： H03M3/02 ,  H03M3/00

CPC分类号： H03M3/344 ,  H03M3/372 ,  H03M3/374 ,  H03M3/43 ,  H03M3/454

摘要： An analogue-to-digital sigma-delta modulator for converting analogue input signals to digital output signals comprises a feedback path (1, 101, 201) for producing analogue feedback signals that are a function of the digital output signals (y, Y), an ‘N’-stage (‘N’≧2) integrator path (9 to 14, 109 to 114) for integrating analogue difference signals that are a difference function of the input signal and the analogue feedback signals, and a quantizer (3, 103) responsive to the signals integrated by the integrator means (9 to 14, 109 to 114) for producing the digital output signals (y, Y) at clock intervals. The feedback path includes ‘N’ feedback stages (15 to 17, 115 to 117) for respective integrator stages (9 to 14, 109 to 114). Each of the ‘N’ feedback stages (15 to 17, 115 to 117) comprises finite impulse response (‘FIR’) filters (15 to 19, 115 to 117), each of the FIR filters being of the same order ‘M’, where ‘M’ is at least two; at least the filter (15, 115) of the feedback stage that feeds back to the first integrator stage is a low pass filter. The integrator stages may be discrete-time integrators; the FIR filters reduce their sensitivity to feedback voltage step changes that would cause non-linearities due to slew-rate limitations. Alternatively, the integrator stages may be continuous-time integrators; the FIR filters reduce their sensitivity to clock pulse jitters. In the embodiment shown in FIG. 11, the first integrator stage (109, 110) is a continuous-time integrator stage, and the remainder of the integrator stages (11 to 14) are discrete-time integrator stages.

摘要翻译： 一种用于将模拟输入信号转换为数字输出信号的模拟 - 数字Σ-Δ调制器包括用于产生作为数字输出信号（y，Y）的函数的模拟反馈信号的反馈路径（1,101,201） 用于对作为输入信号和模拟反馈信号的差分函数的模拟差分信号进行积分的“N”级（“N”= 2）积分器路径（9〜14,109〜114），以及量化器 ，103）响应于由积分器装置（9至14,109至114）积分的信号，用于以时钟间隔产生数字输出信号（y，Y）。 反馈路径包括用于各积分器级（9〜14,109〜114）的“N”个反馈级（15〜17,115〜117）。 “N”个反馈级（15〜17,115〜117）中的每一个包括有限脉冲响应（“FIR”）滤波器（15〜19,115〜117），每个FIR滤波器具有相同的阶数“M” ，其中'M'至少为2; 至少反馈到第一积分器级的反馈级的滤波器（15,115）是低通滤波器。 积分器级可以是离散时间积分器; FIR滤波器降低了对由于压摆率限制导致非线性的反馈电压阶跃变化的敏感性。 或者，积分器级可以是连续时间积分器; FIR滤波器可以降低对时钟脉冲抖动的敏感度。 在