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    Voltage level translator circuit for reducing jitter
    43.
    发明授权
    Voltage level translator circuit for reducing jitter 有权
    用于降低抖动的电压电平转换器电路

    公开(公告)号：US08427223B2

    公开(公告)日：2013-04-23

    申请号：US13186310

    申请日：2011-07-19

    Applicant: Pankaj Kumar ,  Pramod Parameswaran ,  Makeshwar Kothandaraman

    Inventor： Pankaj Kumar ,  Pramod Parameswaran ,  Makeshwar Kothandaraman

    IPC: H03L5/00

    CPC classification number: H03K3/356113

    Abstract: A voltage level translator circuit for translating an input signal referenced to a first voltage supply to an output signal referenced to a second voltage supply includes an input stage for receiving the input signal, the input stage including at least first and second nodes, a voltage at the second node being a logical complement of a voltage at the first node. A load circuit is coupled with the input stage, the load circuit being operative to at least temporarily store a signal at the first and/or second nodes which is indicative of a logical state of the input signal. An output stage connected with the second node is operative to generate an output signal which is indicative of a logical state of the input signal. The voltage level translator circuit further includes a compensation circuit connected with the output stage and operative to balance pull-up and pull-down propagation delays in the voltage level translator circuit as a function of a voltage at the first node.

    Abstract translation: 用于将参考第一电压源的输入信号转换为参考第二电压源的输出信号的电压电平转换器电路包括用于接收输入信号的输入级，输入级至少包括第一和第二节点， 第二节点是第一节点处的电压的逻辑补码。 负载电路与输入级耦合，负载电路可操作以至少临时存储指示输入信号的逻辑状态的第一和/或第二节点处的信号。 与第二节点连接的输出级可操作以产生指示输入信号的逻辑状态的输出信号。 电压电平转换器电路还包括与输出级连接的补偿电路，并且可操作以平衡电压电平转换器电路中的上拉和下拉传播延迟作为第一节点处的电压的函数。

    Impedance Mismatch Detection Circuit
    44.
    发明申请
    Impedance Mismatch Detection Circuit 有权
    阻抗不匹配检测电路

    公开(公告)号：US20130002267A1

    公开(公告)日：2013-01-03

    申请号：US13171725

    申请日：2011-06-29

    Applicant: Makeshwar Kothandaraman ,  Pankaj Kumar ,  Pramod Parameswaran

    Inventor： Makeshwar Kothandaraman ,  Pankaj Kumar ,  Pramod Parameswaran

    IPC: G01R27/28

    CPC classification number: H03F3/45475 ,  H03F2203/45594

    Abstract: A comparison circuit for detecting impedance mismatch between pull-up and pull-down devices in a circuit to be monitored includes a comparator operative to receive first and second signals and to generate, as an output, a third signal indicative of a difference between the first and second signals. A first signal generator is operative to generate the first signal indicative of a difference between reference pull-up and pull-down currents that is scaled by a prescribed amount. The reference pull-up current is indicative of a current flowing through at least one corresponding pull-up transistor device in the circuit to be monitored. The pull-down reference current is indicative of a current flowing through at least one corresponding pull-down transistor device in the circuit to be monitored. A second signal generator connected with the second input of the comparator is operative to generate the second signal as a reference voltage defining a prescribed impedance mismatch threshold associated with the circuit to be monitored.

    Abstract translation: 用于检测待监测电路中的上拉和下拉器件之间的阻抗失配的比较电路包括一个比较器，用于接收第一和第二信号，并产生一个第三信号，该第三信号指示第一和第二信号之间的差值 和第二信号。 第一信号发生器用于产生表示参考上拉和下拉电流之间的差的第一信号，该下拉电流被缩放规定量。 参考上拉电流指示流过待监测电路中的至少一个对应的上拉晶体管器件的电流。 下拉参考电流表示流过待监测电路中的至少一个对应的下拉晶体管器件的电流。 与比较器的第二输入端连接的第二信号发生器可操作以产生第二信号作为参考电压，该参考电压限定与待监视电路相关联的规定阻抗失配阈值。

    AC noise suppression from a bias signal in high voltage supply/low voltage device
    48.
    发明授权
    AC noise suppression from a bias signal in high voltage supply/low voltage device 有权
    高压电源/低压器件偏置信号的交流噪声抑制

    公开(公告)号：US08487691B1

    公开(公告)日：2013-07-16

    申请号：US13494282

    申请日：2012-06-12

    Applicant: Pankaj Kumar ,  Pramod Parameswaran ,  Vani Deshpande ,  Makeshwar Kothandaraman

    Inventor： Pankaj Kumar ,  Pramod Parameswaran ,  Vani Deshpande ,  Makeshwar Kothandaraman

    IPC: G05F1/10

    CPC classification number: H03F1/26 ,  H03F3/2171 ,  H03K19/00346

    Abstract: An apparatus comprising a first circuit, a second circuit, and a third circuit. The first circuit may be configured to generate a first control voltage and a second control voltage. The second circuit may be configured to generate a bias signal in response to the first control voltage and the second control voltage. The third circuit may be configured to generate a filtered signal in response to the bias signal. The filtered signal may be added to the first control voltage and the second control voltage to provide AC noise suppression when generating the bias signal.

    Abstract translation: 一种包括第一电路，第二电路和第三电路的装置。 第一电路可以被配置为产生第一控制电压和第二控制电压。 第二电路可以被配置为响应于第一控制电压和第二控制电压而产生偏置信号。 第三电路可以被配置为响应于偏置信号产生滤波信号。 滤波后的信号可以被添加到第一控制电压和第二控制电压，以在产生偏置信号时提供AC噪声抑制。

    Multicasting Write Requests To Multiple Storage Controllers
    49.
    发明申请
    Multicasting Write Requests To Multiple Storage Controllers 审中-公开
    向多个存储控制器组播写请求

    公开(公告)号：US20110238909A1

    公开(公告)日：2011-09-29

    申请号：US12748764

    申请日：2010-03-29

    Applicant: Pankaj Kumar ,  James A. Mitchell

    Inventor： Pankaj Kumar ,  James A. Mitchell

    IPC: G06F12/16 ,  G06F17/30

    CPC classification number: G06F12/0866 ,  G06F11/1076 ,  G06F2212/262 ,  G06F2212/286

    Abstract: In one embodiment, the present invention includes a method for performing multicasting, including receiving a write request including write data and an address from a first server in a first canister, determining if the address is within a multicast region of a first system memory, and if so, sending the write request directly to the multicast region to store the write data and also to a mirror port of a second canister coupled to the first canister to mirror the write data to a second system memory of the second canister. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，本发明包括一种用于执行多播的方法，包括从第一罐中的第一服务器接收包括写数据和地址的写请求，确定地址是否在第一系统存储器的多播区域内，以及 如果是，则将写入请求直接发送到多播区域以存储写入数据，并将该写请求发送到耦合到第一罐的第二罐的镜像端口，以将写入数据镜像到第二盒的第二系统存储器。 描述和要求保护其他实施例。

    I/O Buffer with Low Voltage Semiconductor Devices
    50.
    发明申请
    I/O Buffer with Low Voltage Semiconductor Devices 失效
    带低压半导体器件的I / O缓冲器

    公开(公告)号：US20100271118A1

    公开(公告)日：2010-10-28

    申请号：US12428556

    申请日：2009-04-23

    Applicant: Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John Kriz ,  Jeffrey Nagy ,  Yehuda Smooha ,  Pankaj Kumar

    Inventor： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John Kriz ,  Jeffrey Nagy ,  Yehuda Smooha ,  Pankaj Kumar

    IPC: G05F1/10

    CPC classification number: H03K17/0822 ,  H03K19/018528

    Abstract: Described embodiments provide for protecting from DC and transient over-voltage conditions an input/output (“I/O”) buffer having first and second I/O transistors. The first I/O transistor is coupled to a first over-voltage protection circuit adapted to prevent an over-voltage condition on at least the first I/O transistor. The second I/O transistor is coupled to a second over-voltage protection circuit adapted to prevent an over-voltage condition on at least the second I/O transistor. First and second bias voltages are generated from an operating voltage of the buffer. A third bias voltage is generated from either i) the first bias voltage, or ii) an output signal voltage of the buffer and a fourth bias voltage is generated from either i) the second bias voltage, or ii) the output signal voltage of the buffer. The third and fourth bias voltages are provided to the first and second over-voltage protection circuits, respectively.

    Abstract translation: 所描述的实施例提供了用于保护具有第一和第二I / O晶体管的输入/输出（“I / O”）缓冲器的DC和瞬态过电压状态。 第一I / O晶体管耦合到适于防止至少第一I / O晶体管上的过电压状态的第一过电压保护电路。 第二I / O晶体管耦合到适于防止至少第二I / O晶体管上的过电压状态的第二过电压保护电路。 从缓冲器的工作电压产生第一和第二偏置电压。 从i）第一偏置电压产生第三偏置电压，或者ii）缓冲器的输出信号电压，以及从i）第二偏置电压产生第四偏置电压，或ii）输出信号电压 缓冲。 第三和第四偏置电压分别提供给第一和第二过压保护电路。

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