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1.发明授权Low power receiver for implementing a high voltage interface implemented with low voltage devices 有权低功率接收器，用于实现采用低电压器件实现的高压接口公开(公告)号：US08847657B2
公开(公告)日：2014-09-30
申请号：US13530426
申请日：2012-06-22
IPC分类号： H03L5/00
CPC分类号： H03L5/00 , H03K19/0013 , H03K19/018507
摘要： An apparatus comprising a first stage and a second stage. The first stage may be configured to generate an intermediate signal having a first voltage in response to an input signal having a second voltage received from a pad. The second stage may be configured to generate a core voltage in response to the first voltage. The voltage received from the pad may operate at a voltage compliant with one or more published interface specifications.
摘要翻译： 一种包括第一级和第二级的装置。 第一级可以被配置为响应于具有从焊盘接收到的第二电压的输入信号而产生具有第一电压的中间信号。 第二级可以被配置为响应于第一电压而产生核心电压。 从焊盘接收的电压可以在符合一个或多个公布的接口规范的电压下工作。
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2.发明授权AC noise suppression from a bias signal in high voltage supply/low voltage device 有权高压电源/低压器件偏置信号的交流噪声抑制公开(公告)号：US08487691B1
公开(公告)日：2013-07-16
申请号：US13494282
申请日：2012-06-12
IPC分类号： G05F1/10
CPC分类号： H03F1/26 , H03F3/2171 , H03K19/00346
摘要： An apparatus comprising a first circuit, a second circuit, and a third circuit. The first circuit may be configured to generate a first control voltage and a second control voltage. The second circuit may be configured to generate a bias signal in response to the first control voltage and the second control voltage. The third circuit may be configured to generate a filtered signal in response to the bias signal. The filtered signal may be added to the first control voltage and the second control voltage to provide AC noise suppression when generating the bias signal.
摘要翻译： 一种包括第一电路，第二电路和第三电路的装置。 第一电路可以被配置为产生第一控制电压和第二控制电压。 第二电路可以被配置为响应于第一控制电压和第二控制电压而产生偏置信号。 第三电路可以被配置为响应于偏置信号产生滤波信号。 滤波后的信号可以被添加到第一控制电压和第二控制电压，以在产生偏置信号时提供AC噪声抑制。
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公开(公告)号：US08427223B2
公开(公告)日：2013-04-23
申请号：US13186310
申请日：2011-07-19
IPC分类号： H03L5/00
CPC分类号： H03K3/356113
摘要： A voltage level translator circuit for translating an input signal referenced to a first voltage supply to an output signal referenced to a second voltage supply includes an input stage for receiving the input signal, the input stage including at least first and second nodes, a voltage at the second node being a logical complement of a voltage at the first node. A load circuit is coupled with the input stage, the load circuit being operative to at least temporarily store a signal at the first and/or second nodes which is indicative of a logical state of the input signal. An output stage connected with the second node is operative to generate an output signal which is indicative of a logical state of the input signal. The voltage level translator circuit further includes a compensation circuit connected with the output stage and operative to balance pull-up and pull-down propagation delays in the voltage level translator circuit as a function of a voltage at the first node.
摘要翻译： 用于将参考第一电压源的输入信号转换为参考第二电压源的输出信号的电压电平转换器电路包括用于接收输入信号的输入级，输入级至少包括第一和第二节点， 第二节点是第一节点处的电压的逻辑补码。 负载电路与输入级耦合，负载电路可操作以至少临时存储指示输入信号的逻辑状态的第一和/或第二节点处的信号。 与第二节点连接的输出级可操作以产生指示输入信号的逻辑状态的输出信号。 电压电平转换器电路还包括与输出级连接的补偿电路，并且可操作以平衡电压电平转换器电路中的上拉和下拉传播延迟作为第一节点处的电压的函数。
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公开(公告)号：US20130002267A1
公开(公告)日：2013-01-03
申请号：US13171725
申请日：2011-06-29
IPC分类号： G01R27/28
CPC分类号： H03F3/45475 , H03F2203/45594
摘要： A comparison circuit for detecting impedance mismatch between pull-up and pull-down devices in a circuit to be monitored includes a comparator operative to receive first and second signals and to generate, as an output, a third signal indicative of a difference between the first and second signals. A first signal generator is operative to generate the first signal indicative of a difference between reference pull-up and pull-down currents that is scaled by a prescribed amount. The reference pull-up current is indicative of a current flowing through at least one corresponding pull-up transistor device in the circuit to be monitored. The pull-down reference current is indicative of a current flowing through at least one corresponding pull-down transistor device in the circuit to be monitored. A second signal generator connected with the second input of the comparator is operative to generate the second signal as a reference voltage defining a prescribed impedance mismatch threshold associated with the circuit to be monitored.
摘要翻译： 用于检测待监测电路中的上拉和下拉器件之间的阻抗失配的比较电路包括一个比较器，用于接收第一和第二信号，并产生一个第三信号，该第三信号指示第一和第二信号之间的差值 和第二信号。 第一信号发生器用于产生表示参考上拉和下拉电流之间的差的第一信号，该下拉电流被缩放规定量。 参考上拉电流指示流过待监测电路中的至少一个对应的上拉晶体管器件的电流。 下拉参考电流表示流过待监测电路中的至少一个对应的下拉晶体管器件的电流。 与比较器的第二输入端连接的第二信号发生器可操作以产生第二信号作为参考电压，该参考电压限定与待监视电路相关联的规定阻抗失配阈值。
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公开(公告)号：US08803535B2
公开(公告)日：2014-08-12
申请号：US13171725
申请日：2011-06-29
CPC分类号： H03F3/45475 , H03F2203/45594
摘要： A comparison circuit for detecting impedance mismatch between pull-up and pull-down devices in a circuit to be monitored includes a comparator operative to receive first and second signals and to generate, as an output, a third signal indicative of a difference between the first and second signals. A first signal generator is operative to generate the first signal indicative of a difference between reference pull-up and pull-down currents that is scaled by a prescribed amount. The reference pull-up current is indicative of a current flowing through at least one corresponding pull-up transistor device in the circuit to be monitored. The pull-down reference current is indicative of a current flowing through at least one corresponding pull-down transistor device in the circuit to be monitored. A second signal generator connected with the second input of the comparator is operative to generate the second signal as a reference voltage defining a prescribed impedance mismatch threshold associated with the circuit to be monitored.
摘要翻译： 用于检测待监测电路中的上拉和下拉器件之间的阻抗失配的比较电路包括一个比较器，用于接收第一和第二信号，并产生一个第三信号，该第三信号指示第一和第二信号之间的差值 和第二信号。 第一信号发生器用于产生表示参考上拉和下拉电流之间的差的第一信号，该下拉电流被缩放规定量。 参考上拉电流指示流过待监测电路中的至少一个对应的上拉晶体管器件的电流。 下拉参考电流表示流过待监测电路中的至少一个对应的下拉晶体管器件的电流。 与比较器的第二输入端连接的第二信号发生器可操作以产生第二信号作为参考电压，该参考电压限定与待监视电路相关联的规定阻抗失配阈值。
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6.发明申请LOW POWER RECEIVER FOR IMPLEMENTING A HIGH VOLTAGE INTERFACE IMPLEMENTED WITH LOW VOLTAGE DEVICES 有权用于实现低电压设备实现的高电压接口的低功率接收器公开(公告)号：US20130342258A1
公开(公告)日：2013-12-26
申请号：US13530426
申请日：2012-06-22
IPC分类号： H03L5/00
CPC分类号： H03L5/00 , H03K19/0013 , H03K19/018507
摘要： An apparatus comprising a first stage and a second stage. The first stage may be configured to generate an intermediate signal having a first voltage in response to an input signal having a second voltage received from a pad. The second stage may be configured to generate a core voltage in response to the first voltage. The voltage received from the pad may operate at a voltage compliant with one or more published interface specifications.
摘要翻译： 一种包括第一级和第二级的装置。 第一级可以被配置为响应于具有从焊盘接收到的第二电压的输入信号而产生具有第一电压的中间信号。 第二级可以被配置为响应于第一电压而产生核心电压。 从焊盘接收的电压可以在符合一个或多个公布的接口规范的电压下工作。
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公开(公告)号：US08816748B2
公开(公告)日：2014-08-26
申请号：US13494188
申请日：2012-06-12
IPC分类号： H03L5/00
CPC分类号： H03K3/356113 , H03K3/013
摘要： An apparatus comprising a level shifter circuit and a control circuit. The level shifter circuit may be configured to generate a differential output in response to (i) a first differential input, (ii) a second differential input and (iii) a first supply. The level shifter circuit comprises a first pull down transistor pair operating with the first supply. The control circuit may be configured to generate the second differential input in response to (i) the first differential input and (ii) a second supply. The control circuit generally comprises a second pull down transistor pair operating with the second supply. The first supply has a higher voltage than the second supply.
摘要翻译： 一种包括电平移位器电路和控制电路的装置。 电平移位器电路可以被配置为响应于（i）第一差分输入，（ii）第二差分输入和（iii）第一电源而产生差分输出。 电平移位器电路包括与第一电源一起工作的第一下拉晶体管对。 控制电路可以被配置为响应于（i）第一差分输入和（ii）第二电源而产生第二差分输入。 控制电路通常包括与第二电源一起工作的第二下拉晶体管对。 第一个电源具有比第二个电源更高的电压。
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公开(公告)号：US20130328611A1
公开(公告)日：2013-12-12
申请号：US13494188
申请日：2012-06-12
IPC分类号： H03L5/00
CPC分类号： H03K3/356113 , H03K3/013
摘要： An apparatus comprising a level shifter circuit and a control circuit. The level shifter circuit may be configured to generate a differential output in response to (i) a first differential input, (ii) a second differential input and (iii) a first supply. The level shifter circuit comprises a first pull down transistor pair operating with the first supply. The control circuit may be configured to generate the second differential input in response to (i) the first differential input and (ii) a second supply. The control circuit generally comprises a second pull down transistor pair operating with the second supply. The second supply has a higher voltage than the first supply.
摘要翻译： 一种包括电平移位器电路和控制电路的装置。 电平移位器电路可以被配置为响应于（i）第一差分输入，（ii）第二差分输入和（iii）第一电源而产生差分输出。 电平移位器电路包括与第一电源一起工作的第一下拉晶体管对。 控制电路可以被配置为响应于（i）第一差分输入和（ii）第二电源而产生第二差分输入。 控制电路通常包括与第二电源一起工作的第二下拉晶体管对。 第二个电源具有比第一个电源更高的电压。
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公开(公告)号：US08598941B2
公开(公告)日：2013-12-03
申请号：US13165195
申请日：2011-06-21
申请人： Dipankar Bhattacharya , Ashish V. Shukla , John Christopher Kriz , Makeshwar Kothandaraman , Pankaj Kumar , Pramod Parameswaran
发明人： Dipankar Bhattacharya , Ashish V. Shukla , John Christopher Kriz , Makeshwar Kothandaraman , Pankaj Kumar , Pramod Parameswaran
IPC分类号： H01L37/00
CPC分类号： H03F3/3022 , H03F1/308 , H03F1/56 , H03F2200/447
摘要： A compensation circuit for controlling a variation in output impedance of at least one buffer circuit includes a monitor circuit and a control circuit coupled with the monitor circuit. The monitor circuit includes a pull-up portion including at least one PMOS transistor and a pull-down portion comprising at least one NMOS transistor. The monitor circuit is configured to track an operation of an output stage of the buffer circuit and is operative to generate at least a first control signal indicative of a status of at least one characteristic of corresponding pull-up and pull-down portions in the output stage of the buffer circuit over variations in PVT conditions to which the buffer circuit may be subjected. The control circuit is operative to generate a set of digital control bits as a function of the first control signal. The set of digital control bits is operative to compensate the pull-up and pull-down portions in the output stage of the buffer circuit over prescribed variations in PVT conditions.
摘要翻译： 用于控制至少一个缓冲电路的输出阻抗变化的补偿电路包括监视电路和与监视器电路耦合的控制电路。 监视器电路包括上拉部分，其包括至少一个PMOS晶体管和包括至少一个NMOS晶体管的下拉部分。 监视器电路被配置为跟踪缓冲电路的输出级的操作，并且可操作地产生至少第一控制信号，该第一控制信号指示输出中相应的上拉和下拉部分的至少一个特性的状态 缓冲电路的阶段与缓冲电路可能受到的PVT条件的变化有关。 控制电路用于产生作为第一控制信号的函数的一组数字控制位。 该组数字控制位可用来补偿缓冲电路的输出级中的上拉和下拉部分超过规定的PVT条件变化。
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公开(公告)号：US20120326768A1
公开(公告)日：2012-12-27
申请号：US13165195
申请日：2011-06-21
申请人： Dipankar Bhattacharya , Ashish V. Shukla , John Christopher Kriz , Makeshwar Kothandaraman , Pankaj Kumar , Pramod Parameswaran
发明人： Dipankar Bhattacharya , Ashish V. Shukla , John Christopher Kriz , Makeshwar Kothandaraman , Pankaj Kumar , Pramod Parameswaran
IPC分类号： H03H11/40
CPC分类号： H03F3/3022 , H03F1/308 , H03F1/56 , H03F2200/447
摘要： A compensation circuit for controlling a variation in output impedance of at least one buffer circuit includes a monitor circuit and a control circuit coupled with the monitor circuit. The monitor circuit includes a pull-up portion including at least one PMOS transistor and a pull-down portion comprising at least one NMOS transistor. The monitor circuit is configured to track an operation of an output stage of the buffer circuit and is operative to generate at least a first control signal indicative of a status of at least one characteristic of corresponding pull-up and pull-down portions in the output stage of the buffer circuit over variations in PVT conditions to which the buffer circuit may be subjected. The control circuit is operative to generate a set of digital control bits as a function of the first control signal. The set of digital control bits is operative to compensate the pull-up and pull-down portions in the output stage of the buffer circuit over prescribed variations in PVT conditions.
摘要翻译： 用于控制至少一个缓冲电路的输出阻抗变化的补偿电路包括监视电路和与监视器电路耦合的控制电路。 监视器电路包括上拉部分，其包括至少一个PMOS晶体管和包括至少一个NMOS晶体管的下拉部分。 监视器电路被配置为跟踪缓冲电路的输出级的操作，并且可操作地产生至少第一控制信号，该第一控制信号指示输出中相应的上拉和下拉部分的至少一个特性的状态 缓冲电路的阶段与缓冲电路可能受到的PVT条件的变化有关。 控制电路用于产生作为第一控制信号的函数的一组数字控制位。 该组数字控制位可用来补偿缓冲电路的输出级中的上拉和下拉部分超过规定的PVT条件变化。
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