公开(公告)号：US20210132999A1

公开(公告)日：2021-05-06

申请号：US17084392

申请日：2020-10-29

Applicant: Rambus Inc.

Inventor： Christopher Haywood ,  Evan Lawrence Erickson

IPC: G06F9/50 ,  G06F9/451 ,  G06F12/1072 ,  G06F12/02 ,  G06F12/1009

Abstract: A memory allocation device for deployment within a host server computer includes control circuitry, a first interface to a local processing unit disposed within the host computer and local operating memory disposed within the host computer, and a second interface to a remote computer. The control circuitry allocates a first portion of the local memory to a first process executed by the local processing unit and transmits, to the remote computer via the second interface, a request to allocate to a second process executed by the local processing unit a first portion of a remote memory disposed within the remote computer. The control circuitry further receives instructions via the first interface to store data at a memory address within the first portion of the remote memory and transmits those instructions to the remote computer via the second interface.

公开(公告)号：US20250103508A1

公开(公告)日：2025-03-27

申请号：US18812262

申请日：2024-08-22

Applicant: Rambus Inc.

Inventor： Evan Lawrence Erickson ,  Taeksang Song ,  Christopher Haywood

IPC: G06F12/1009 ,  G06F12/02 ,  G06F13/16

Abstract: Described are computational systems in which hosts share pooled memory on the same memory module. A memory buffer with access to the pooled memory manages which regions of the memory are allocated to the different hosts such that memory regions, and thus the data they contain, can be exchanged between hosts. Unidirectional or bidirectional data exchanges between hosts swap regions of equal size so the amount of memory allocated to each host is not changed as a result of the exchange.

公开(公告)号：US12135645B2

公开(公告)日：2024-11-05

申请号：US18203569

申请日：2023-05-30

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Christopher Haywood

IPC: G06F12/0804 ,  G06F12/12 ,  G11C14/00

Abstract: A hybrid volatile/non-volatile memory module employs a relatively fast, durable, and expensive dynamic, random-access memory (DRAM) cache to store a subset of data from a larger amount of relatively slow and inexpensive nonvolatile memory (NVM). A module controller prioritizes accesses to the DRAM cache for improved speed performance and to minimize programming cycles to the NVM. Data is first written to the DRAM cache where it can be accessed (written to and read from) without the aid of the NVM. Data is only written to the NVM when that data is evicted from the DRAM cache to make room for additional data. Mapping tables relating NVM addresses to physical addresses are distributed throughout the DRAM cache using cache line bits that are not used for data.

公开(公告)号：US20240311219A1

公开(公告)日：2024-09-19

申请号：US18591545

申请日：2024-02-29

Applicant: Rambus Inc.

Inventor： Christopher Haywood

IPC: G06F11/07

CPC classification number: G06F11/0751 ,  G06F11/073

Abstract: Technologies for providing write protection to an integrated circuit memory device are described. The integrated circuit memory device has an input port to receive write data and command data and a read data output port to send read data. A device includes a write protection mechanism to prevent write data from being written to a memory core. The write protection mechanism can mask the write data or abort a write operation in response to activation. The write protection mechanism can be activated in response to an error detected by a serial data buffer (SDB) device coupled to the integrated circuit memory device.

公开(公告)号：US20240256131A1

公开(公告)日：2024-08-01

申请号：US18412840

申请日：2024-01-15

Applicant: Rambus Inc.

Inventor： Christopher Haywood

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0673

Abstract: A serial data buffer integrated circuit comprises unidirectional host-side input and output ports, and unidirectional memory-side input and output ports. Scheduling logic generates memory device commands for writing to and reading from a memory device based on a set of host-side input packets received from a memory controller. A unidirectional serial host side input port receives host-side input packets from the memory controller. A unidirectional serial memory side output port transmits the memory device commands and the write data to the memory device based on the scheduled timing. A unidirectional serial memory side input port receives read data from the memory device in response to a read command, and a unidirectional serial host side output port transmits the read data to the memory controller within the timing constraints of the memory device.

公开(公告)号：US20240201894A1

公开(公告)日：2024-06-20

申请号：US18540670

申请日：2023-12-14

Applicant: Rambus Inc.

Inventor： Evan Lawrence Erickson ,  Christopher Haywood

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0673

Abstract: An apparatus and method for low page overhead recompression. In one embodiment a memory buffer integrated circuit (IC) device is disclosed that includes a first circuit configured to independently compress equally sized portions of a page of data, and a second circuit configured to store the compressed data portions at respective addresses in memory. The memory buffer IC device also includes a third circuit configured to store a page table comprising an entry with information related to the respective memory addresses.

公开(公告)号：US20240012565A1

公开(公告)日：2024-01-11

申请号：US18218831

申请日：2023-07-06

Applicant: Rambus Inc.

Inventor： Evan Lawrence Erickson ,  Christopher Haywood ,  Craig E. Hampel

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0673

Abstract: A buffer integrated circuit (IC) chip is disclosed. The buffer IC chip includes host interface circuitry to receive a request from at least one host. The request includes at least one command to perform a memory compression operation on first uncompressed data that is stored in a first memory region. Compression circuitry, in response to the at least one command, compresses the first uncompressed data to first compressed data. The first compressed data is transferred to a second memory region.

公开(公告)号：US20230359559A1

公开(公告)日：2023-11-09

申请号：US18203569

申请日：2023-05-30

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Christopher Haywood

IPC: G06F12/0804 ,  G06F12/12

CPC classification number: G06F12/0804 ,  G06F12/12 ,  G06F2212/1044 ,  G06F2212/205 ,  G11C14/0018

Abstract: A hybrid volatile/non-volatile memory module employs a relatively fast, durable, and expensive dynamic, random-access memory (DRAM) cache to store a subset of data from a larger amount of relatively slow and inexpensive nonvolatile memory (NVM). A module controller prioritizes accesses to the DRAM cache for improved speed performance and to minimize programming cycles to the NVM. Data is first written to the DRAM cache where it can be accessed (written to and read from) without the aid of the NVM. Data is only written to the NVM when that data is evicted from the DRAM cache to make room for additional data. Mapping tables relating NVM addresses to physical addresses are distributed throughout the DRAM cache using cache line bits that are not used for data.

公开(公告)号：US11804277B2

公开(公告)日：2023-10-31

申请号：US17722667

申请日：2022-04-18

Applicant: Rambus Inc.

Inventor： Christopher Haywood

IPC: G11C29/44 ,  G11C29/18 ,  G11C29/12 ,  G11C7/22 ,  G11C29/00

CPC classification number: G11C29/44 ,  G11C7/22 ,  G11C29/12015 ,  G11C29/18 ,  G11C29/702 ,  G11C2029/1806

Abstract: Many error correction schemes fail to correct for double-bit errors and a module must be replaced when these double-bit errors occur repeatedly at the same address. This helps prevent data corruption. In an embodiment, the addresses for one of the memory devices exhibiting a single-bit error (but not the other also exhibiting a single bit error) is transformed before the internal memory arrays are accessed. This has the effect of moving one of the error prone memory cells to a different external (to the module) address such that there is only one error prone bit that is accessed by the previously double-bit error prone address. Thus, a double-bit error at the original address is remapped into two correctable single-bit errors that are at different addresses.

公开(公告)号：US20230315656A1

公开(公告)日：2023-10-05

申请号：US18116266

申请日：2023-03-01

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Christopher Haywood

IPC: G06F13/16 ,  G06F13/40

CPC classification number: G06F13/1689 ,  G06F13/4068

Abstract: In a modular memory system, a memory control component, first and second memory sockets and data buffer components are all mounted to the printed circuit board. The first and second memory sockets have electrical contacts to electrically engage counterpart electrical contacts of memory modules to be inserted therein, and each of the data buffer components includes a primary data interface electrically coupled to the memory control component, and first and second secondary data interfaces electrically coupled to subsets of the electrical contacts within the first and second memory sockets, respectively.