公开(公告)号：US07173664B2

公开(公告)日：2007-02-06

申请号：US10208588

申请日：2002-07-30

申请人： Tohru Watanabe ,  Takashi Tanimoto ,  Tatsuya Takahashi

发明人： Tohru Watanabe ,  Takashi Tanimoto ,  Tatsuya Takahashi

IPC分类号： H04N5/225

CPC分类号： H04N5/23241 ,  H04N5/335

摘要： An image signal processor for reducing power consumption. The image signal processor is connected between a solid-state imaging device, which generates a first image signal, and an external device, and includes first and second regulators, a switch circuit, a signal processing circuit, and an output circuit. The first regulator generates a first voltage that is in accordance with an output level of the solid-state imaging device. The second regulator generates a second voltage that is in accordance with an input level of the external device. The switch circuit supplies the power supply voltage or the second voltage to the output circuit in accordance with the operating state of the imaging external device. The signal processing circuit operates with the first voltage and generates a second image signal. The output circuit provides the second image signal to the external device.

摘要翻译： 一种用于降低功耗的图像信号处理器。 图像信号处理器连接在产生第一图像信号的固态成像装置和外部装置之间，并且包括第一和第二调节器，开关电路，信号处理电路和输出电路。 第一调节器产生与固态成像装置的输出电平相一致的第一电压。 第二调节器产生与外部设备的输入电平相对应的第二电压。 开关电路根据成像外部设备的操作状态将电源电压或第二电压提供给输出电路。 信号处理电路以第一电压工作并产生第二图像信号。 输出电路将第二图像信号提供给外部设备。

公开(公告)号：US20060233431A1

公开(公告)日：2006-10-19

申请号：US11426754

申请日：2006-06-27

申请人： Tohru Watanabe

发明人： Tohru Watanabe

IPC分类号： H04N17/02 ,  G06K9/00

CPC分类号： G09G3/006 ,  G06T5/005 ,  G06T5/20 ,  G06T7/0002 ,  G09G2330/10 ,  H01L27/14806 ,  H04N5/21 ,  H04N5/367 ,  H04N5/3675

摘要： A deficiency candidate detection circuit detects a deficient pixel candidate by comparing the image signal of a target pixel with the image signals of peripheral pixels, and address information of the deficient pixel candidate is stored in a position memory circuit. A deficiency determining circuit repeats the determination of a deficient pixel a number of times based on the address information stored in the position memory circuit, and determines address information of a deficient pixel from the continuity of the determination results. A deficiency registering circuit registers the determined address information in the position memory circuit. A deficiency correction circuit corrects the image signal of the deficient pixel according to the registered address information of the deficient pixel.

摘要翻译： 不足候选检测电路通过将目标像素的图像信号与周边像素的图像信号进行比较来检测缺陷像素候选，并且将不良像素候选的地址信息存储在位置存储电路中。 缺陷判定电路基于存储在位置存储电路中的地址信息重复不良像素的判定次数，根据判定结果的连续性来判定缺陷像素的地址信息。 缺陷登记电路将确定的地址信息登记在位置存储电路中。 缺陷校正电路根据缺陷像素的注册地址信息校正缺陷像素的图像信号。

公开(公告)号：US20060232691A1

公开(公告)日：2006-10-19

申请号：US11426759

申请日：2006-06-27

申请人： Tohru Watanabe

发明人： Tohru Watanabe

IPC分类号： H04N9/64

CPC分类号： G09G3/006 ,  G06T5/005 ,  G06T5/20 ,  G06T7/0002 ,  G09G2330/10 ,  H01L27/14806 ,  H04N5/21 ,  H04N5/367 ,  H04N5/3675

摘要： A deficiency candidate detection circuit detects a deficient pixel candidate by comparing the image signal of a target pixel with the image signals of peripheral pixels, and address information of the deficient pixel candidate is stored in a position memory circuit. A deficiency determining circuit repeats the determination of a deficient pixel a number of times based on the address information stored in the position memory circuit, and determines address information of a deficient pixel from the continuity of the determination results. A deficiency registering circuit registers the determined address information in the position memory circuit. A deficiency correction circuit corrects the image signal of the deficient pixel according to the registered address information of the deficient pixel.

公开(公告)号：US07092018B1

公开(公告)日：2006-08-15

申请号：US09696393

申请日：2000-10-25

申请人： Tohru Watanabe

发明人： Tohru Watanabe

IPC分类号： H04N9/64 ,  G06K9/38 ,  H04N1/04

CPC分类号： G09G3/006 ,  G06T5/005 ,  G06T5/20 ,  G06T7/0002 ,  G09G2330/10 ,  H01L27/14806 ,  H04N5/21 ,  H04N5/367 ,  H04N5/3675

摘要： A deficiency candidate detection circuit detects a deficient pixel candidate by comparing the image signal of a target pixel with the image signals of peripheral pixels, and address information of the deficient pixel candidate is stored in a position memory circuit. A deficiency determining circuit repeats the determination of a deficient pixel a number of times based on the address information stored in the position memory circuit, and determines address information of a deficient pixel from the continuity of the determination results. A deficiency registering circuit registers the determined address information in the position memory circuit. A deficiency correction circuit corrects the image signal of the deficient pixel according to the registered address information of the deficient pixel.

摘要翻译： 不足候选检测电路通过将目标像素的图像信号与周边像素的图像信号进行比较来检测缺陷像素候选，并且将不良像素候选的地址信息存储在位置存储电路中。 缺陷判定电路基于存储在位置存储电路中的地址信息重复不良像素的判定次数，根据判定结果的连续性来判定缺陷像素的地址信息。 缺陷登记电路将确定的地址信息登记在位置存储电路中。 缺陷校正电路根据缺陷像素的注册地址信息校正缺陷像素的图像信号。

公开(公告)号：US20060012686A1

公开(公告)日：2006-01-19

申请号：US10531768

申请日：2003-12-10

申请人： Tohru Watanabe

发明人： Tohru Watanabe

IPC分类号： H04N5/228

CPC分类号： G06T1/00

摘要： A first processing circuit subjects image data output from an A/D converter circuit to a first signal process to produce first image data. A second processing circuit subjects image data to a second signal process, which is independent of the first signal process, to produce second image data. The first and second processing circuits execute the first and second signal processes in a parallel manner to output the first and second image data to a display device and a system microcomputer.

摘要翻译： 第一处理电路将从A / D转换器电路输出的图像数据作为第一信号处理，以产生第一图像数据。 第二处理电路使图像数据进入与第一信号处理无关的第二信号处理，以产生第二图像数据。 第一和第二处理电路以并行方式执行第一和第二信号处理，以将第一和第二图像数据输出到显示装置和系统微计算机。

公开(公告)号：US06351284B1

公开(公告)日：2002-02-26

申请号：US08719439

申请日：1996-09-25

申请人： Tohru Watanabe ,  Shuichi Nakano

发明人： Tohru Watanabe ,  Shuichi Nakano

IPC分类号： H04N5335

CPC分类号： H04N5/335 ,  H01L27/14812 ,  H01L27/14887

摘要： A method and apparatus for driving a solid state image sensor are disclosed. The method and apparatus operate such that the amount of information charges remaining in channel regions at the time of transferring the information charge packets from the channel regions is significantly reduced. The solid state image sensor being driven has a semiconductor substrate, at least one layer of which is located over the semiconductor substrate and where channel regions are formed, and gate electrodes are formed over the semiconductor substrate to respectively cover the channel regions. Drain regions are also defined in the semiconductor substrate respectively adjacent to the channel regions in either a lateral direction or a vertical direction. Each channel region is capable of storing information charges. The driving device for the described solid state image sensor includes: a first control voltage generator for applying a first control voltage to one of the gate electrodes in a predetermined period to form a potential well in at least one of the channel regions; and a second control voltage generator for applying a second control voltage to the semiconductor substrate defining the drain regions in the predetermined period so as to set the potential barrier lower than the preset height in order to temporarily restrict an amount of the information charges to be stored in the potential well.

摘要翻译： 公开了一种用于驱动固态图像传感器的方法和装置。 所述方法和装置的操作使得在从信道区域传送信息计费数据包时剩余在信道区域中的信息量的量显着减少。 被驱动的固态图像传感器具有半导体衬底，其至少一层位于半导体衬底上并且形成沟道区，并且在半导体衬底上形成栅电极以分别覆盖沟道区。 在半导体衬底中也限定了在横向或垂直方向上分别与沟道区相邻的漏极区。 每个通道区域都能够存储信息费用。 用于所述固态图像传感器的驱动装置包括：第一控制电压发生器，用于以预定周期向一个栅电极施加第一控制电压，以在至少一个沟道区中形成势阱; 以及第二控制电压发生器，用于在预定时间段内向限定漏区的半导体衬底施加第二控制电压，以将势垒设置为低于预设高度，以暂时限制要存储的信息电荷量 在潜力很好。

公开(公告)号：US06288744B1

公开(公告)日：2001-09-11

申请号：US08555118

申请日：1995-11-08

申请人： Hideki Takahashi ,  Tohru Watanabe

发明人： Hideki Takahashi ,  Tohru Watanabe

IPC分类号： H04N314

CPC分类号： H04N5/3452 ,  H04N5/37213

摘要： The invention is intended to provide a highly integrated solid-state image pickup device, in which the number of transfer electrodes of a horizontal shift register is reduced, and a plurality of vertical shifter registers are arranged with a reduced pitch therebetween. Output-control gate electrodes are disposed at an output end of the vertical shift registers. These output-control gate electrodes are operated independently from vertical transfer gate electrodes, and temporarily reserve information charges. Horizontal transfer gate electrodes corresponding to the vertical shift registers on odd-numbered columns are turned on, so signals charges in these vertical shift registers are read into a horizontal shift register. During horizontal transfer of these information charges, information charges of vertical shift registers on even-numbered columns are reserved, for half of a horizontal scanning period, in output ends of the vertical shift registers by the output-control gate electrodes. Thereafter, the information charges in the vertical shift registers on the even-numbered columns are read into the horizontal shift register, and are horizontally transferred. Since one horizontal transfer operation requires half of the pixels per row, the horizontal shift regiter includes two transfer electrodes for each vertical shift register.

摘要翻译： 本发明旨在提供一种高度集成的固态图像拾取装置，其中水平移位寄存器的转移电极的数量减少，并且多个垂直移位寄存器之间以缩小的间距排列。 输出控制栅电极设置在垂直移位寄存器的输出端。 这些输出控制栅电极独立于垂直传输栅极电极工作，并暂时保留信息电荷。 对应于奇数列上的垂直移位寄存器的水平传输门电极导通，因此这些垂直移位寄存器中的信号电荷被读入水平移位寄存器。 在这些信息电荷的水平传送期间，通过输出控制栅电极在垂直移位寄存器的输出端保留偶数列上的垂直移位寄存器的信息电荷，占水平扫描周期的一半。 此后，偶数列上的垂直移位寄存器中的信息电荷被读入水平移位寄存器，并被水平传送。 由于一个水平传送操作需要每行的一半像素，所以水平移位调节器包括用于每个垂直移位寄存器的两个传送电极。

公开(公告)号：US5703641A

公开(公告)日：1997-12-30

申请号：US414756

申请日：1995-03-31

申请人： Tohru Watanabe

发明人： Tohru Watanabe

IPC分类号： H01L31/0216 ,  H04N9/04 ,  H04N9/083 ,  H04N9/07

CPC分类号： H04N9/083 ,  H01L31/02162 ,  H04N9/045

摘要： A solid-state color image pickup device which is capable of simplifying signal processing with respect to picture signals. A color filter mounted on the solid-state image pickup device is composed of first to fourth filter elements E1 to E4. The sum E1+E2 of the signals of color components obtained by adding the color components of the first filter element E1 and the second filter element E2 which are disposed in an odd-numbered row is equal to the sum E3+E4 of the signal of color components obtained by adding the color components of the third filter element E3 and the fourth filter element E4 which are disposed in an even-numbered row. A brightness signal having color components in a predetermined ratio is obtained for each of E1+E2, and E3+E4. A color component signal representing one of the three primary colors (R, G, B) of light is represented by the difference between the color component signals of the first filter element E1 and the second filter element E2, and the difference between the color component signals of the third filter element E3 and the fourth filter element E4. Thus, signals necessary for producing a color image are obtained for each row of light-receiving picture elements.

摘要翻译： 一种固态彩色图像拾取装置，其能够简化关于图像信号的信号处理。 安装在固态图像拾取装置上的滤色器由第一至第四滤色器元件E1至E4组成。 通过将配置在奇数行中的第一滤波器元件E1和第二滤波器元件E2的颜色分量相加而获得的颜色分量的信号的和E1 + E2与信号的信号的和+ E3 + E4的和 通过添加配置在偶数行中的第三滤波器元件E3和第四滤波器元件E4的颜色分量而获得的颜色分量。 对于E1 + E2和E3 + E4中的每一个，获得具有预定比率的颜色分量的亮度信号。 表示光的三原色（R，G，B）中的一种的颜色分量信号由第一滤光器元件E1和第二滤光器元件E2的颜色分量信号之间的差异以及颜色分量 第三滤波器元件E3和第四滤波器元件E4的信号。 因此，对于每行受光图像元素获得产生彩色图像所需的信号。

公开(公告)号：US5544091A

公开(公告)日：1996-08-06

申请号：US205844

申请日：1994-03-02

申请人： Tohru Watanabe

发明人： Tohru Watanabe

IPC分类号： G06F17/10 ,  H04N7/14 ,  G06F7/38

CPC分类号： H04N7/147 ,  G06F17/10

摘要： For input signals f0-f7, by the implementing of signal processing in several stages with bit-serial form, output signals f0-f7 are obtained. For input signals f0-f7, non-two's power approximation proportions of ideal values of fixed coefficient, i.e., cos[.pi.l(2K+1)/2N] are applied. This results in asymmetrical hardware to implement a forward transform mode and an inverse transform mode. Therefore, by adding a circuit element which is employed for a forward transform mode, and by adding a circuit element which is employed for an inverse transform mode, hardware which can deal with both of forward transform and inverse transform is realized.

摘要翻译： 对于输入信号f0-f7，通过以位串行形式实现数个级的信号处理，获得输出信号f0-f7。 对于输入信号f0-f7，施加固定系数的理想值的非二次方的功率近似比例，即cosπ（2K + 1）/ 2N]。 这导致不对称硬件实现正向变换模式和逆变换模式。 因此，通过添加用于正向变换模式的电路元件，并且通过添加用于逆变换模式的电路元件，实现了可以处理正向变换和逆变换两者的硬件。

公开(公告)号：US5398459A

公开(公告)日：1995-03-21

申请号：US156641

申请日：1993-11-24

申请人： Katsuya Okumura ,  Tohru Watanabe ,  Riichirou Aoki ,  Hiroyuki Yano ,  Masako Kodera ,  Atsushi Shigeta ,  You Ishii ,  Norio Kimura ,  Masayoshi Hirose ,  Yukio Ikeda

发明人： Katsuya Okumura ,  Tohru Watanabe ,  Riichirou Aoki ,  Hiroyuki Yano ,  Masako Kodera ,  Atsushi Shigeta ,  You Ishii ,  Norio Kimura ,  Masayoshi Hirose ,  Yukio Ikeda

IPC分类号： B24B37/10 ,  B24B37/30 ,  B24B1/00

CPC分类号： B24B37/102 ,  B24B37/30

摘要： A workpiece such as a semiconductor wafer is positioned between a turntable and a top ring and polished by an abrasive cloth on the turntable while the top ring is being pressed against the turntable. The top ring has a retaining ring for preventing the workpiece from deviating from the lower surface of the top ring, and the retaining ring has an inside diameter larger than an outside diameter of the workpiece. The rotation of the turntable imparts a pressing force in a direction parallel to the upper surface of the turntable to the workpiece so that an outer periphery of the workpiece contacts an inner periphery of the retaining ring, and the rotation of the retaining ring imparts a rotational force to the workpiece so that the workpiece performs a planetary motion relative to the top ring in the retaining ring.

摘要翻译： 诸如半导体晶片的工件位于转盘和顶环之间，并且当顶环被压靠在转盘上时，其通过研磨布在转盘上抛光。 顶环具有用于防止工件偏离顶环的下表面的保持环，并且保持环的内径大于工件的外径。 转台的转动使平台于转台上表面的方向向工件施加压力，使得工件的外周与保持环的内周接触，并且保持环的旋转赋予转动 使工件相对于保持环中的顶环执行行星运动。