公开(公告)号：US08835994B2

公开(公告)日：2014-09-16

申请号：US12791372

申请日：2010-06-01

申请人： Joseph Ervin ,  Jeffrey B. Johnson ,  Paul C. Parries ,  Chengwen Pei ,  Geng Wang ,  Yanli Zhang

发明人： Joseph Ervin ,  Jeffrey B. Johnson ,  Paul C. Parries ,  Chengwen Pei ,  Geng Wang ,  Yanli Zhang

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L29/786 ,  H01L27/12 ,  H01L21/84 ,  H01L29/66 ,  H01L27/108 ,  H01L21/762

CPC分类号： H01L21/76283 ,  H01L21/84 ,  H01L27/1087 ,  H01L27/10873 ,  H01L27/1203 ,  H01L29/66181 ,  H01L29/78603 ,  H01L29/78609 ,  H01L29/78696 ,  H01L29/945

摘要： A structural alternative to retro doping to reduce transistor leakage is provided by providing a liner in a trench, undercutting a conduction channel region in an active semiconductor layer, etching a side, corner and/or bottom of the conduction channel where the undercut exposes semiconductor material in the active layer and replacing the removed portion of the conduction channel with insulator. This shaping of the conduction channel increases the distance to adjacent circuit elements which, if charged, could otherwise induce a voltage and cause a change in back-channel threshold in regions of the conduction channel and narrows and reduces cross-sectional area of the channel where the conduction in the channel is not well-controlled; both of which effects significantly reduce leakage of the transistor.

公开(公告)号：US20110291169A1

公开(公告)日：2011-12-01

申请号：US12791372

申请日：2010-06-01

申请人： Joseph Ervin ,  Jeffrey B. Johnson ,  Paul C. Parries ,  Chengwen Pei ,  Geng Wang ,  Yanli Zhang

发明人： Joseph Ervin ,  Jeffrey B. Johnson ,  Paul C. Parries ,  Chengwen Pei ,  Geng Wang ,  Yanli Zhang

IPC分类号： H01L27/12 ,  H01L21/86 ,  H01L29/78

CPC分类号： H01L21/76283 ,  H01L21/84 ,  H01L27/1087 ,  H01L27/10873 ,  H01L27/1203 ,  H01L29/66181 ,  H01L29/78603 ,  H01L29/78609 ,  H01L29/78696 ,  H01L29/945

摘要： A structural alternative to retro doping to reduce transistor leakage is provided by providing a liner in a trench, undercutting a conduction channel region in an active semiconductor layer, etching a side, corner and/or bottom of the conduction channel where the undercut exposes semiconductor material in the active layer and replacing the removed portion of the conduction channel with insulator. This shaping of the conduction channel increases the distance to adjacent circuit elements which, if charged, could otherwise induce a voltage and cause a change in back-channel threshold in regions of the conduction channel and narrows and reduces cross-sectional area of the channel where the conduction in the channel is not well-controlled; both of which effects significantly reduce leakage of the transistor.

摘要翻译： 通过在沟槽中提供衬垫，切割有源半导体层中的导电沟道区域，蚀刻导电沟道的侧面，拐角和/或底部，其中底切暴露半导体材料来提供用于减少晶体管泄漏的复古掺杂的结构替代方案 在有源层中，用绝缘体代替导电沟道的去除部分。 传导通道的这种整形增加了相邻电路元件的距离，如果充电，电荷可能会导致电压并导致导通通道区域中的反向通道阈值的变化并且减小了通道的横截面积 通道的传导不能很好地控制; 这两种效应显着降低了晶体管的泄漏。

公开(公告)号：US08298884B2

公开(公告)日：2012-10-30

申请号：US12862048

申请日：2010-08-24

申请人： Geng Wang ,  Joseph Ervin ,  Jeffrey B. Johnson ,  Paul C. Parries

发明人： Geng Wang ,  Joseph Ervin ,  Jeffrey B. Johnson ,  Paul C. Parries

IPC分类号： H01L21/338

CPC分类号： H01L29/66772 ,  H01L21/2652 ,  H01L29/78696

摘要： The present disclosure provides a semiconductor device that may include a substrate including a semiconductor layer overlying an insulating layer. A gate structure that is present on a channel portion of the semiconductor layer. A first dopant region is present in the channel portion of the semiconductor layer, in which the peak concentration of the first dopant region is present within the lower portion of the gate conductor and the upper portion of the semiconductor layer. A second dopant region is present in the channel portion of the semiconductor layer, in which the peak concentration of the second dopant region is present within the lower portion of the semiconductor layer.

摘要翻译： 本公开提供了一种半导体器件，其可以包括包括覆盖绝缘层的半导体层的衬底。 存在于半导体层的沟道部分上的栅极结构。 第一掺杂区存在于半导体层的沟道部分中，其中第一掺杂区的峰值浓度存在于栅极导体的下部和半导体层的上部之间。 第二掺杂剂区域存在于半导体层的沟道部分中，其中第二掺杂剂区域的峰值浓度存在于半导体层的下部。

公开(公告)号：US08133781B2

公开(公告)日：2012-03-13

申请号：US12705768

申请日：2010-02-15

申请人： Joseph Ervin ,  Geng Wang

发明人： Joseph Ervin ,  Geng Wang

IPC分类号： H01L21/8242 ,  H01L21/20 ,  H01L21/425

CPC分类号： H01L21/84 ,  H01L21/2652 ,  H01L27/1087 ,  H01L27/1203 ,  H01L29/66181 ,  H01L29/78 ,  H01L29/945

摘要： A mask layer formed over a semiconductor substrate is lithographically patterned to form an opening therein. Ions are implanted at an angle that is normal to the surface of the semiconductor substrate through the opening and into an upper portion of the semiconductor substrate. Straggle of the implanted ions form a doped region that laterally extends beyond a horizontal cross-sectional area of the opening. A deep trench is formed by performing an anisotropic etch of a semiconductor material underneath the opening to a depth above a deep end of an implanted region. Ion implantation steps and anisotropic etch steps are alternately employed to extend the depth of the doped region and the depth of the deep trench, thereby forming a doped region around a deep trench that has narrow lateral dimensions. The doped region can be employed as a buried plate for a deep trench capacitor.

摘要翻译： 在半导体衬底上形成的掩模层被光刻图案化以在其中形成开口。 离子以与半导体衬底的表面垂直的角度通过开口注入并进入半导体衬底的上部。 注入离子的束缚形成横向延伸超过开口的水平横截面积的掺杂区域。 通过对开口下方的半导体材料进行向注入区域的深端上方的深度的各向异性蚀刻来形成深沟槽。 交替使用离子注入步骤和各向异性蚀刻步骤来扩展掺杂区域的深度和深沟槽的深度，从而在具有窄横向尺寸的深沟槽周围形成掺杂区域。 掺杂区域可以用作深沟槽电容器的掩埋板。

公开(公告)号：US20120049295A1

公开(公告)日：2012-03-01

申请号：US12862048

申请日：2010-08-24

申请人： Geng Wang ,  Joseph Ervin ,  Jeffrey B. Johnson ,  Paul C. Parries

发明人： Geng Wang ,  Joseph Ervin ,  Jeffrey B. Johnson ,  Paul C. Parries

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66772 ,  H01L21/2652 ,  H01L29/78696

摘要： The present disclosure provides a semiconductor device that may include a substrate including a semiconductor layer overlying an insulating layer. A gate structure that is present on a channel portion of the semiconductor layer. A first dopant region is present in the channel portion of the semiconductor layer, in which the peak concentration of the first dopant region is present within the lower portion of the gate conductor and the upper portion of the semiconductor layer. A second dopant region is present in the channel portion of the semiconductor layer, in which the peak concentration of the second dopant region is present within the lower portion of the semiconductor layer.

公开(公告)号：US20110201161A1

公开(公告)日：2011-08-18

申请号：US12705768

申请日：2010-02-15

申请人： Joseph Ervin ,  Geng Wang

发明人： Joseph Ervin ,  Geng Wang

IPC分类号： H01L21/02 ,  H01L21/336

CPC分类号： H01L21/84 ,  H01L21/2652 ,  H01L27/1087 ,  H01L27/1203 ,  H01L29/66181 ,  H01L29/78 ,  H01L29/945

摘要： A mask layer formed over a semiconductor substrate is lithographically patterned to form an opening therein. Ions are implanted at an angle that is normal to the surface of the semiconductor substrate through the opening and into an upper portion of the semiconductor substrate. Straggle of the implanted ions form a doped region that laterally extends beyond a horizontal cross-sectional area of the opening. A deep trench is formed by performing an anisotropic etch of a semiconductor material underneath the opening to a depth above a deep end of an implanted region. Ion implantation steps and anisotropic etch steps are alternately employed to extend the depth of the doped region and the depth of the deep trench, thereby forming a doped region around a deep trench that has narrow lateral dimensions. The doped region can be employed as a buried plate for a deep trench capacitor.

摘要翻译： 在半导体衬底上形成的掩模层被光刻图案化以在其中形成开口。 离子以与半导体衬底的表面垂直的角度通过开口注入并进入半导体衬底的上部。 注入离子的束缚形成横向延伸超过开口的水平横截面积的掺杂区域。 通过对开口下方的半导体材料进行向注入区域的深端上方的深度的各向异性蚀刻来形成深沟槽。 交替使用离子注入步骤和各向异性蚀刻步骤来扩展掺杂区域的深度和深沟槽的深度，从而在具有窄横向尺寸的深沟槽周围形成掺杂区域。 掺杂区域可以用作深沟槽电容器的掩埋板。

公开(公告)号：US08536649B2

公开(公告)日：2013-09-17

申请号：US13608860

申请日：2012-09-10

申请人： Geng Wang ,  Joseph Ervin ,  Jeffrey B. Johnson ,  Paul C. Parries

发明人： Geng Wang ,  Joseph Ervin ,  Jeffrey B. Johnson ,  Paul C. Parries

IPC分类号： H01L29/66

CPC分类号： H01L29/66772 ,  H01L21/2652 ,  H01L29/78696

摘要： The present disclosure provides a semiconductor device that may include a substrate including a semiconductor layer overlying an insulating layer. A gate structure that is present on a channel portion of the semiconductor layer. A first dopant region is present in the channel portion of the semiconductor layer, in which the peak concentration of the first dopant region is present within the lower portion of the gate conductor and the upper portion of the semiconductor layer. A second dopant region is present in the channel portion of the semiconductor layer, in which the peak concentration of the second dopant region is present within the lower portion of the semiconductor layer.

摘要翻译： 本公开提供了一种半导体器件，其可以包括包括覆盖绝缘层的半导体层的衬底。 存在于半导体层的沟道部分上的栅极结构。 第一掺杂区存在于半导体层的沟道部分中，其中第一掺杂区的峰值浓度存在于栅极导体的下部和半导体层的上部之间。 第二掺杂剂区域存在于半导体层的沟道部分中，其中第二掺杂剂区域的峰值浓度存在于半导体层的下部。

公开(公告)号：US20120326233A1

公开(公告)日：2012-12-27

申请号：US13608860

申请日：2012-09-10

申请人： Geng Wang ,  Joseph Ervin ,  Jeffrey B. Johnson ,  Paul C. Parries

发明人： Geng Wang ,  Joseph Ervin ,  Jeffrey B. Johnson ,  Paul C. Parries

IPC分类号： H01L29/78

CPC分类号： H01L29/66772 ,  H01L21/2652 ,  H01L29/78696

摘要： The present disclosure provides a semiconductor device that may include a substrate including a semiconductor layer overlying an insulating layer. A gate structure that is present on a channel portion of the semiconductor layer. A first dopant region is present in the channel portion of the semiconductor layer, in which the peak concentration of the first dopant region is present within the lower portion of the gate conductor and the upper portion of the semiconductor layer. A second dopant region is present in the channel portion of the semiconductor layer, in which the peak concentration of the second dopant region is present within the lower portion of the semiconductor layer.

摘要翻译： 本公开提供了一种半导体器件，其可以包括包括覆盖绝缘层的半导体层的衬底。 存在于半导体层的沟道部分上的栅极结构。 第一掺杂区存在于半导体层的沟道部分中，其中第一掺杂区的峰值浓度存在于栅极导体的下部和半导体层的上部之间。 第二掺杂剂区域存在于半导体层的沟道部分中，其中第二掺杂剂区域的峰值浓度存在于半导体层的下部内。

公开(公告)号：US08692307B2

公开(公告)日：2014-04-08

申请号：US13530519

申请日：2012-06-22

申请人： Joseph Ervin ,  Brian Messenger ,  Karen A. Nummy ,  Ravi M. Todi

发明人： Joseph Ervin ,  Brian Messenger ,  Karen A. Nummy ,  Ravi M. Todi

IPC分类号： H01L27/108

CPC分类号： H01L28/60 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66181 ,  H01L29/945

摘要： Deep trench capacitor structures and methods of manufacture are disclosed. The method includes forming a deep trench structure in a wafer comprising a substrate, buried oxide layer (BOX) and silicon (SOI) film. The structure includes a wafer comprising a substrate, buried insulator layer and a layer of silicon on insulator layer (SOI) having a single crystalline structure throughout the layer. The structure further includes a first plate in the substrate and an insulator layer in direct contact with the first plate. A doped polysilicon is in direct contact with the insulator layer and also in direct contact with the single crystalline structure of the SOI.

摘要翻译： 公开了深沟槽电容器结构和制造方法。 该方法包括在包括衬底，掩埋氧化物层（BOX）和硅（SOI））膜的晶片中形成深沟槽结构。 该结构包括晶片，其包括衬底，掩埋绝缘体层和在整个层中具有单晶结构的绝缘体上硅层（SOI）层。 该结构还包括基板中的第一板和与第一板直接接触的绝缘体层。 掺杂多晶硅与绝缘体层直接接触，并且与SOI的单晶结构直接接触。

公开(公告)号：US08232163B2

公开(公告)日：2012-07-31

申请号：US12916864

申请日：2010-11-01

申请人： Joseph Ervin ,  Brian Messenger ,  Karen A. Nummy ,  Ravi M. Todi

发明人： Joseph Ervin ,  Brian Messenger ,  Karen A. Nummy ,  Ravi M. Todi

IPC分类号： H01L21/8242

CPC分类号： H01L28/60 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66181 ,  H01L29/945

摘要： Deep trench capacitor structures and methods of manufacture are disclosed. The method includes forming a deep trench structure in a wafer comprising a substrate, buried oxide layer (BOX) and silicon (SOI) film. The method further includes forming a plate on a sidewall of the deep trench structure in the substrate by an implant process. The implant processes contaminate exposed edges of the SOI film in the deep trench structure. The method further includes removing the contaminated exposed edges of the SOI film by an etching process to form a void in the SOI film. The method further includes growing epitaxial Si in the void, prior to completing a capacitor structure.

摘要翻译： 公开了深沟槽电容器结构和制造方法。 该方法包括在包括衬底，掩埋氧化物层（BOX）和硅（SOI））膜的晶片中形成深沟槽结构。 该方法还包括通过植入工艺在衬底中的深沟槽结构的侧壁上形成板。 植入工艺污染了深沟槽结构中SOI膜的暴露边缘。 该方法还包括通过蚀刻工艺去除SOI膜的污染的暴露边缘，以在SOI膜中形成空隙。 该方法还包括在完成电容器结构之前在空隙中生长外延Si。