公开(公告)号：US06834016B2

公开(公告)日：2004-12-21

申请号：US10421139

申请日：2003-04-23

申请人： Daisuke Kato ,  Yohji Watanabe

发明人： Daisuke Kato ,  Yohji Watanabe

IPC分类号： G11C700

CPC分类号： G11C29/787

摘要： A semiconductor memory device having a memory system and a redundancy system including redundant elements for repairing a plurality of defects in the memory system, comprising a plurality of address fuse sets each including address fuses for programming a defective address in the memory system, and a master fuse for preventing a corresponding redundant element from being selected when the redundant element is not used, wherein at least one master fuse is shared by at least two fuse sets among the plurality of address fuse sets.

摘要翻译： 一种具有存储器系统和冗余系统的半导体存储器件，包括用于修复存储器系统中的多个缺陷的冗余元件，包括多个地址熔丝组，每个地址熔丝组包括用于对存储器系统中的缺陷地址进行编程的地址熔丝，以及主器件 用于防止在不使用所述冗余元件时选择相应的冗余元件的熔丝，其中至少一个主熔丝由所述多个地址熔丝组中的至少两个熔丝组共享。

公开(公告)号：US06711648B1

公开(公告)日：2004-03-23

申请号：US08825311

申请日：1997-03-28

申请人： Peter Poechmueller ,  Yohji Watanabe

发明人： Peter Poechmueller ,  Yohji Watanabe

IPC分类号： G06F1200

CPC分类号： G11C7/1072 ,  G11C7/1033 ,  G11C7/1048

摘要： The present invention includes a cost efficient method of substantially increasing the data bandwidth of a dynamic random access memory (DRAM) device initially configured to operate in an extended data output (EDO) mode, the EDO DRAM device including at least one storage cell, a column decoder, an internal read/write data bus and an off chip driver latch, the column decoder decoding a column address upon receipt thereof such that data stored in the at least one storage cell corresponding to the decoded column addresses is placed on the internal read/write data bus in response to the receipt of an address transition detection (ATD) pulse generated by the dynamic memory device and further wherein output data is stored in the off chip driver latch in response to a transfer pulse. The method includes the steps of temporarily suppressing the generation of the ATD pulse such that data selected from the at least one storage cell is not placed on internal read/write data bus until after a delayed generation of the ATD pulse in response to the falling edge of a column address strobe (CAS) signal, such that a first pipeline stage is thereby substantially defined.

摘要翻译： 本发明包括一种基本上增加动态随机存取存储器（DRAM）装置的数据带宽的成本有效的方法，该动态随机存取存储器（DRAM）装置最初被配置为以扩展数据输出（EDO）模式工作，该EDO DRAM装置包括至少一个存储单元， 列解码器，内部读/写数据总线和芯片外驱动器锁存器，列解码器在接收到列地址时解码列地址，使得存储在与解码列地址对应的至少一个存储单元中的数据被放置在内部读 响应于接收到由动态存储器件产生的地址转换检测（ATD）脉冲写入数据总线，并且其中响应于传送脉冲将输出数据存储在片外驱动器锁存器中。 该方法包括以下步骤：暂时抑制ATD脉冲的产生，使得从至少一个存储单元中选择的数据不会置于内部读/写数据总线上，直到响应于下降沿延迟产生ATD脉冲为止 列地址选通（CAS）信号，从而基本上限定第一流水线级。

公开(公告)号：US06301144B1

公开(公告)日：2001-10-09

申请号：US09650745

申请日：2000-08-30

申请人： Munehiro Yoshida ,  Yohji Watanabe

发明人： Munehiro Yoshida ,  Yohji Watanabe

IPC分类号： G11C700

CPC分类号： G11C7/1057 ,  G11C7/10 ,  G11C7/1051

摘要： A memory chip is comprises memory cells and, for example, 16 amplifiers, each having a first output terminal and a second output terminal. The 16 amplifiers are connected at the first output terminal to 16 first-type signal lines RD(0) to RD(15) and at the second output terminal to four second-type signal lines bTRD(0) to bTRD(3) in increment fashion. More precisely, the second output terminals of every four amplifiers are connected the four second-type signal lines, respectively. A coincidence/non-coincidence determining circuit determines how the potentials of the second-type signal lines bTRD(0) to bTRD(3) and the potentials of the first-type signal lines RD(0) to RD(15) connected to all amplifiers that are connected to the second-type signal lines change when all data items of the same polarity are read from memory cells. Hence, a compressed-data test can be performed thereby compressing 16-bit data into 4-bit data by using only 20 signal lines.

摘要翻译： 存储器芯片包括存储器单元和例如16个放大器，每个具有第一输出端子和第二输出端子。 16个放大器在第一输出端子连接到16个第一类型信号线RD（0）至RD（15），在第二输出端连接到四个第二类型信号线bTRD（0）至bTRD（3） 时尚。 更准确地说，每四个放大器的第二输出端分别连接四个第二类信号线。 一致/不一致确定电路确定第二类型信号线bTRD（0）至bTRD（3）的电位和第一类信号线RD（0）至RD（15）的电位如何连接到所有 当从存储器单元读取相同极性的所有数据项时，连接到第二类型信号线的放大器改变。 因此，可以执行压缩数据测试，从而通过仅使用20个信号线将16位数据压缩成4位数据。

公开(公告)号：US6108254A

公开(公告)日：2000-08-22

申请号：US150782

申请日：1993-11-12

申请人： Yohji Watanabe ,  Kenji Tsuchida

发明人： Yohji Watanabe ,  Kenji Tsuchida

IPC分类号： G11C11/409 ,  G11C7/06 ,  G11C7/10 ,  G11C11/407

CPC分类号： G11C7/106 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096 ,  G11C7/1006 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/22

摘要： A Dynamic Random Access Memory (DRAM) in which a data input/output buffer is connected between first data lines and second data lines. An equalizing circuit and a data latch circuit are connected to the second data lines. The equalizing circuit maintains the second data lines in reset condition, during normal operation. It temporarily releases the second data lines from the reset condition, in response to an output from an address-transition detecting circuit, thereby to transfer the data from the data input/output buffer. The data latch circuit latches the data transferred to the second data lines, in response to the output from the address-transition detecting circuit.

摘要翻译： 动态随机存取存储器（DRAM），其中数据输入/输出缓冲器连接在第一数据线和第二数据线之间。 均衡电路和数据锁存电路连接到第二数据线。 均衡电路在正常工作期间将第二条​​数据线保持在复位状态。 它响应于地址转换检测电路的输出暂时从复位状态释放第二数据线，从而从数据输入/输出缓冲器传送数据。 数据锁存电路根据地址转换检测电路的输出锁存传送到第二数据线的数据。

公开(公告)号：US5933371A

公开(公告)日：1999-08-03

申请号：US105052

申请日：1998-06-26

申请人： Yohji Watanabe

发明人： Yohji Watanabe

IPC分类号： G11C7/10 ,  G11C7/00

CPC分类号： G11C7/1048 ,  G11C7/1078

摘要： In a DQ write amplifier, a data line DQ is precharged and driven by one P-channel MOS transistor and a data line /DQ is precharged and driven by one P-channel MOS transistor. These transistors are controlled by a control circuit composed of NAND circuits and inverters. In the DQ write amplifier, a transition is made from the precharge state to the write state through the use of only a write signal applied to the control circuit.

摘要翻译： 在DQ写放大器中，数据线DQ由一个P沟道MOS晶体管预充电和驱动，数据线/ DQ由一个P沟道MOS晶体管预充电和驱动。 这些晶体管由由NAND电路和反相器构成的控制电路来控制。 在DQ写放大器中，通过仅使用施加到控制电路的写入信号，从预充电状态转变为写入状态。

公开(公告)号：US5289413A

公开(公告)日：1994-02-22

申请号：US712106

申请日：1991-06-07

申请人： Kenji Tsuchida ,  Yohji Watanabe

发明人： Kenji Tsuchida ,  Yohji Watanabe

IPC分类号： G11C7/10 ,  G11C8/00

CPC分类号： G11C7/1033 ,  G11C7/1006

摘要： A MOS memory device includes an array of rows and columns of memory cells, word lines connected to the rows of memory cells, and a plurality of pairs of bits lines connected to the columns. Sense amplifiers and transfer gates are provided for every bit line pair. A column decoder has outputs connected via column-select lines to transfer gates such that each output is connected to two adjacent gates. When activating a certain column, the column decoder potentially activates another column adjacent to the certain column before actually receiving the corresponding column address. This permits information bits stored in four memory cells to be transferred simultaneously to the registers and latched therein. A multiplexer serially reads out the latched information bits. The column preactivation improves the serial accessing speed of the memory device.

摘要翻译： MOS存储器件包括存储器单元的行和列的阵列，连接到存储器单元的行的字线以及连接到列的多对位线。 为每个位线对提供感测放大器和传输门。 列解码器具有通过列选择线连接的输出以传送门，使得每个输出连接到两个相邻的门。 当激活某个列时，列解码器在实际接收相应的列地址之前潜在地激活与特定列相邻的另一列。 这允许存储在四个存储单元中的信息位同时传送到寄存器并锁存在其中。 多路复用器串行读出锁存的信息位。 列预激活提高了存储设备的串行访问速度。